Clock Trace Routing: Length and Termination

Why a Clock Is Different

A clock is a periodic signal that runs at a single frequency, and that changes how it behaves compared with a data line. Its energy is concentrated at the fundamental and its harmonics rather than spread over a band, so a resonance or a stub at a harmonic frequency produces a discrete peak that shows up in an emission measurement and in a receiver’s sensitivity test. Its edges are often fast, which means its effective bandwidth is much higher than its clock rate suggests, and the return current follows the trace beneath it rather than spreading through the plane. Routing a clock like an ordinary signal is the origin of a large share of EMC problems.

Reference and Return Path

The clock should be routed on a layer adjacent to a solid reference plane, and the plane should be unbroken for the whole length of the trace. Where the trace crosses a split in the reference, the return current has to divert around the gap, which enlarges the loop and turns the trace into a radiator. Where the clock must change layers, a stitching via or a capacitor should be placed next to the transition so that the return current has a path, and the reference planes on the two layers should be the same net. The return path is the most common and the most expensive clock routing error, and it is invisible on a schematic.

Stubs and Branches

Any branch off the clock line is a stub, and a stub behaves as a resonant element that reflects energy at a frequency set by its length. A short stub to a single load is negligible, a stub to a test point can be significant, and a stub that is a quarter wavelength long is a serious problem. The rule is to keep the stub length short compared with the wavelength of the highest harmonic of interest, and to avoid branching the clock to several loads on a single line where the branches are long. Where several devices need the clock, a point-to-point topology with a buffer or a clock distribution device is more predictable than a long T or a star.

Length, Skew and Matching

Where the clock is part of a synchronous interface, the length of the clock line determines when the receiving device samples the data, so the clock and the data lines are matched to a defined relationship. The matching is different for a source-synchronous interface, where the clock and data travel together and are matched to each other, and for a common-clock interface, where the clock is delivered separately and the length budget includes both the clock and the data paths. The numbers come from the interface specification, not from a general rule, and the propagation delay per unit length comes from the actual stackup rather than from an estimate. Where the length cannot be achieved, the answer is usually to change the routing or add a delay element rather than to accept a timing margin.

Termination

A clock line that is long relative to the rise time needs termination, because otherwise the reflection returns as a double edge that a receiver can misinterpret and that radiates. Series termination at the source is the usual choice for a point-to-point clock, since it limits the current and damps the reflection while consuming little power. Parallel termination at the far end is used where the line is long and the current is affordable, and a Thevenin or an AC termination where the power budget matters. The resistor should be placed at the source or at the end of the line, not in the middle, and its value should be matched to the line impedance rather than chosen from a stock value.

Guarding and Crosstalk

A clock couples into whatever runs beside it, and the coupling is proportional to the parallel length and inversely proportional to the spacing. A clock running parallel to an analog input or a sensitive reset line for a long distance will couple into it regardless of the impedance matching. The remedies are to increase the spacing, to route the clock on a layer between planes where the fields are contained, to keep the parallel length short, and to cross other signals at right angles where they must cross at all. Where a clock must run beside a sensitive line, a grounded guard trace stitched to the plane with vias along its length reduces the coupling, at the cost of board area.

The Clock as an EMI Source

Because the clock is periodic, it produces emissions at its harmonics, and because it is usually the fastest periodic signal on the board, it is often the dominant source. The layout levers are the loop area, the return path, the length of the trace and the edge rate. Reducing the edge rate at the source, where the device allows it, reduces the harmonic content directly and is often the single most effective change. Where the clock leaves the board, the cable becomes part of the antenna, and filtering or a shielded connector at the boundary is the answer.

Clocks and Test Access

A clock is also the signal most likely to be disturbed by test access. A test point or a probe pad placed on a clock line adds capacitance and a stub, and the add-on can be enough to change the timing or to create a reflection that the receiver sees as an extra edge. Where the clock must be probed, the access should be short, placed as close to the source as the constraints allow, and removed from the production design if the fixture permits it. The same logic applies to a via used as a probe point: it is a stub, and its length should be counted in the stub budget. Where the interface is critical, the test strategy should be decided together with the routing rather than added after the layout is complete, since a probe point that cannot be placed is a test that cannot be run.

FAQ

Why is the clock more critical than other signals? Because it is periodic, so its energy is concentrated at discrete frequencies and its fast edges give it a high effective bandwidth.

Can I split the reference plane under a clock? No. The return current must have a continuous path, or the loop area grows and the trace radiates.

How long can a stub be? Short compared with the wavelength of the highest harmonic of interest. A stub near a quarter wavelength resonates and reflects.

Do I always need termination? Where the line is long relative to the rise time, yes. Series termination at the source is the commonest choice.

How do I stop a clock coupling into other traces? Increase the spacing, reduce the parallel length, route it between planes, cross at right angles and use a stitched guard trace where necessary.

Conclusion

A clock is a periodic, fast-edged signal, so it should be routed over a continuous reference, kept free of stubs and branches, terminated when the line is long and matched to whatever interface it belongs to. Power and signal integrity rules are part of PCB design and layout, the stackup that provides the reference is agreed under PCB capabilities, and the emissions are confirmed during PCBA testing. High-speed boards of this kind are normally characterised through prototype PCB assembly in 2026.