Decoupling Capacitor Placement and Loop Area

What Decoupling Does

A decoupling capacitor is a local reservoir of charge that supplies a switching device while the power distribution network is still responding. When a logic gate switches, it draws a current pulse in a few hundred picoseconds, and the inductance of the path back to the regulator means the current cannot arrive that fast from a distant source. The capacitor supplies it locally, and the voltage at the device stays inside its tolerance. What makes the capacitor effective is therefore not its capacitance alone but the inductance of the loop it forms with the device and the planes, because that inductance sets how quickly the charge can be delivered.

Distance Versus Loop Area

The usual advice is to place the capacitor as close to the device pin as possible, and the reason is loop area rather than distance as such. The current leaves the device, travels to the capacitor and returns through the ground, and the area enclosed by that path determines the inductance. A capacitor placed 2 mm away but connected with a short, wide, direct path can have a smaller loop than one placed 1 mm away with a long, narrow, indirect connection. Placing the capacitor on the opposite side of the board directly under the power pin is often the smallest loop of all, because the via through the board is short and the planes complete the return path immediately.

Via Placement and Inductance

The vias that connect the capacitor to the power and ground planes are part of the loop, and their inductance often exceeds the inductance of the capacitor itself. Two short vias next to each other are much better than two long vias at opposite ends of the pad, and putting both vias on the same side of the capacitor body, close together, reduces the loop further. Where the planes are far apart in the stack, the via has to travel further, which is one of the reasons a thin dielectric between the power and ground planes is valuable: it shortens the return path for every decoupling current in the design at once.

The Plane Pair as a Capacitor

A closely spaced power and ground plane pair behaves as a distributed capacitor, and at high frequency it does much of the decoupling work. Its capacitance is proportional to the area and to the dielectric constant and inversely proportional to the separation, so a thin dielectric between the planes gives a useful capacitance across the whole board. This is why a stackup with the power plane adjacent to a ground plane is worth the layer, and why the discrete capacitors matter most at the frequencies where the plane’s own inductance and the spreading inductance of the plane begin to dominate. Treating the plane pair as part of the decoupling network, rather than as a passive conductor, is what makes a high-speed design work.

Value and Package Choice

Larger capacitance is not automatically better, because a larger capacitor in the same package has a lower self-resonant frequency, above which it behaves inductively and stops helping. The practical approach is a set of values arranged so that their self-resonances overlap, which gives a low impedance over a broad band, and packages chosen for low inductance rather than for small size alone. A small package with a short internal path can be more effective than a larger one with more capacitance, because the loop it forms with the planes is smaller. The measured impedance of the network, rather than the sum of the capacitor values, is what determines the result.

Placement Rules

Place a capacitor for every power pin that switches, or share one between two adjacent pins of the same rail. Keep the connection to the planes as short and as wide as possible, with the vias close together and on the same side of the part. Keep the loop between the capacitor and the device small, even at the cost of absolute distance. Use the plane pair deliberately in the stackup, with the power plane adjacent to a ground plane. Where a design has a large device with many rails, place the small, high-frequency capacitors nearest the pins and the bulk capacitors further away, since the bulk ones are needed at lower frequencies where the loop inductance matters less.

Common Mistakes

The recurring errors are placing capacitors by rote at a uniform spacing regardless of where the current is drawn, connecting them with long narrow traces to the planes, using a single value for every position, and leaving the power and ground planes far apart in the stack. Another is treating the decoupling capacitors as a substitute for a good plane structure, when in fact the planes do most of the work above a few tens of megahertz. A design that is failing its power integrity targets is more often fixed by changing the stackup or the via arrangement than by adding capacitance.

Decoupling and the Device Package

The package itself is part of the loop. A device with a large body and long internal lead frames adds inductance between the die and the board, and no amount of capacitance on the board can compensate for a package that cannot deliver charge to the die quickly. This is why fine-pitch and land-grid packages are preferred for high-speed devices, and why the capacitor placement pattern changes with the package type: for a quad flat pack the capacitors go beside the pins, while for a ball grid array they go directly underneath, on the opposite side of the board, where the via from the ball to the plane is the shortest possible connection. The design should also consider the reference plane the charge returns through, since a split in the plane under a large device forces the return current to divert and destroys the benefit of a close capacitor.

FAQ

How close should a decoupling capacitor be? Close enough that the loop it forms with the device and the planes is small. Loop area matters more than the distance in millimetres.

Does a bigger capacitor decouple better? Not necessarily. A larger capacitance in the same package has a lower self-resonance and can be less effective at high frequency.

Why put the vias on the same side? To minimise the loop area between the capacitor and the planes, which is where most of the inductance comes from.

Do the planes matter? Yes, a closely spaced power and ground plane pair provides distributed capacitance and does much of the decoupling at high frequency.

Should I use one value everywhere? No. A spread of values with overlapping self-resonances gives a lower impedance over a wider band.

Conclusion

Decoupling is an inductance problem before it is a capacitance problem, so the placement, the via arrangement and the plane structure matter more than the value on the label. Keep the loop small, use the plane pair deliberately, choose packages for low inductance and place the capacitors where the current is drawn. Power integrity is part of PCB design and layout, the plane structure belongs to the stackup described under PCB manufacturing capability, and the resulting noise behaviour is confirmed during PCBA testing. High-speed boards are normally characterised through prototype PCB assembly in 2026.