Crystal Oscillator vs Active Clock in PCB Design

Every digital design has at least one clock, and the component that generates it is often chosen in a hurry. A passive crystal and an active oscillator are both sold as clocks, they occupy a similar footprint, and their behaviour is quite different in ways that matter for accuracy, startup and layout.

Two Different Devices

A passive crystal is a quartz resonator with two terminals. It does not oscillate on its own. It is placed in a feedback loop around an amplifier that is built into the processor, and the combination produces the clock. The designer supplies the crystal, the two load capacitors and the layout, and the chip supplies the drive.

An active oscillator contains the resonator and the amplifier in one package, with a supply pin and an output pin. It produces a finished clock waveform and needs nothing from the processor except power. That difference in who owns the circuit is the origin of most of the other differences between them.

Accuracy and Stability

The accuracy of a passive crystal is set by the resonator and by the load capacitance the designer places around it. Get the capacitance wrong and the frequency shifts, which is why the load capacitance figure on the datasheet is a target to be met by the layout and not a suggestion.

An active oscillator is trimmed at manufacture and specified with a total stability figure that includes temperature, ageing and supply variation. Where the product needs a guaranteed accuracy over its life, that single figure is much easier to design against than the accumulation of several contributions on the passive side. The consequences of getting a timing figure wrong appear in the interfaces described in our high speed routing article.

Startup Behaviour

A passive crystal takes time to reach its frequency after power is applied, because the loop has to build amplitude from noise. That startup time is specified and can be milliseconds, which matters if the processor is released from reset before the clock is stable.

Many processors therefore include a startup delay in their power sequence, and the crystal specification has to fit inside it. An active oscillator starts much faster in most cases, which is one reason it is chosen in designs that must be operational quickly.

Jitter and Phase Noise

Jitter is the variation in the position of the clock edges, and it is what limits high speed serial interfaces. A passive crystal in a well designed loop has excellent jitter performance because the resonator is doing the work directly.

An active oscillator can be equal or better, but its performance depends on the internal circuit and on the supply noise it sees. For serial interfaces running at high rates, the oscillator datasheet will state a jitter figure, and that figure should be compared against the budget the interface allows rather than assumed adequate.

Layout Requirements

The layout for a passive crystal is a small circuit and must be treated as one. The crystal and its capacitors belong as close to the processor pins as possible, with short traces and a ground plane beneath them.

No other signal should be routed through that area. A clock is a low level analog signal at that point, and a switching trace nearby will couple into it and pull the frequency or add jitter. Guarding the area with ground and keeping it clear of the power supply switching node is standard practice, and the cost of doing so is a few square millimetres. Our PCB layout notes describe the general spacing discipline that applies.

Cost and Part Availability

A passive crystal is cheaper than an active oscillator, and it is available in more frequencies and package sizes. Where the design can tolerate the accuracy and the startup behaviour, it is the lower cost choice and the one most designers reach for by default.

An active oscillator costs more but removes the capacitor selection and the sensitive layout. Where board area is tight, where the accuracy requirement is strict or where several clocks must be distributed with a defined skew, that trade often favours the oscillator. Both parts are commodity items, so availability is rarely the deciding factor.

Distribution of Multiple Clocks

Where a board needs several clocks, they can be generated separately or derived from one source. Deriving them from one source gives a defined phase relationship, which some interfaces require, but it also means a single failure takes all of them down.

Clock buffers used for distribution must be chosen for jitter as well as for fan out. A buffer that adds more jitter than the receiving interface can tolerate converts a good source into an unusable clock, and the datasheet figure is the only way to know before the board is built. Our notes on transmission lines describe how the distribution traces should be treated.

Choosing Between Them

The decision reduces to four questions. How accurate must the clock be over temperature and life, how quickly must it be running after power is applied, how much jitter can the interface tolerate, and how much board area and layout effort is available.

Where all four answers are undemanding, a passive crystal is the right choice. Where any of them is tight, an active oscillator usually repays its cost in layout freedom and in a specification that can be met without measurement. Recording which of the four drove the decision is what makes the choice reviewable in a later revision. Our component tolerance and reliability article describes how such decisions are documented.

Phase Jitter and What It Costs the Interface

Phase jitter is the deviation of the clock edge from where it should be, and every high speed serial interface has a budget for it. Part of that budget is allocated to the clock source, part to the channel and part to the receiver, and the source figure is the one the designer controls by choosing the device.

A passive crystal with a well laid out loop usually has excellent phase jitter, because the resonator is directly responsible for the timing. An active oscillator states its figure on the datasheet, which makes the budget arithmetic straightforward but does not guarantee a better result. What matters is that the number is compared against the allowance rather than assumed adequate. Our high speed routing notes describe the rest of the budget.

Clock Layout Rules That Matter

Clock layout comes down to keeping the sensitive loop small and keeping everything else away from it. The crystal, its loading capacitors and the device pins form a loop that should occupy as little area as possible, with a ground plane beneath it and no other signal routed through that area.

The supply to the oscillator should be decoupled locally, because noise on that rail modulates the clock. Where a clock is distributed across the board, its traces should be treated as controlled impedance lines referenced to a continuous plane, and they should be kept away from switching nodes and from connector edges. A clock that is quiet on the bench can radiate efficiently once it reaches a cable, which is the problem described in our EMC design techniques article.

FAQ

Can any crystal be used with any processor? No. The processor specifies a frequency range, a load capacitance and a maximum equivalent series resistance, and the crystal must satisfy all three.

Do load capacitors need to be exact? They need to be close, because their value shifts the frequency. The datasheet figure accounts for the capacitance of the traces as well, so layout matters.

Is an oscillator always more accurate? Usually, because it is trimmed and specified as a complete unit. A well designed crystal circuit can be equally accurate at lower cost.