DDR3 vs DDR4 PCB: Routing and Stack-Up Differences

Why the Memory Interface Sets the Board

The DRAM interface is usually the fastest parallel bus on a board, and it is the one that decides the layer count, the stack-up and much of the routing budget. It is also unforgiving: a memory bus that works at room temperature and fails after ten minutes of operation, or works on one board and not on the next, is almost always a signal integrity or a power integrity problem rather than a component problem.

DDR3 and DDR4 look similar in the schematic and behave differently on the board. The changes that matter are the data rate, the reference voltage and the topology the controller expects, and a design that treats DDR4 as a faster DDR3 will spend the project chasing timing failures.

The Electrical Differences That Change the Layout

• Data rate. DDR3 runs from about 800 to 2133 megatransfers per second, while DDR4 starts where DDR3 ends and runs to 3200 and beyond. Higher rates shrink the unit interval, so the same physical length mismatch costs more of the timing budget.
• Supply voltage. DDR3 uses 1.5 volts, or 1.35 volts in the low voltage version, while DDR4 runs at 1.2 volts. The lower swing reduces the noise margin in absolute terms, which puts more pressure on the reference plane and on crosstalk.
• Termination. DDR3 requires a termination rail, typically half the supply, with its own regulator and its own decoupling for the address, command and control nets. DDR4 moves the termination onto the die and adds a separate 2.5 volt supply for the DRAM array, so the board no longer needs the VTT rail but does need the VPP rail and its own decoupling.
• Reference voltage. DDR3 requires an external reference for the input threshold, which is a sensitive analogue node that has to be clean. DDR4 generates the reference internally for the data pins, which removes one board level concern but leaves the address and command reference to be handled.
• Bank structure and burst. DDR4 has more bank groups and a different burst behaviour, which changes the access pattern and therefore the pattern of current the board has to deliver.

Topology

The largest layout difference is the topology the controller expects. DDR3 at lower speeds can use a T-branch, where the address and command nets run to a central point and then split to each device, so that every device sees a similar delay. As the rate rises, that structure becomes hard to control, because each branch is a stub and the reflections from the stubs close the timing window.

DDR4 uses a fly-by topology: the address, command and control signals daisy chain past each DRAM in turn, and the resulting delay difference between devices is compensated by write leveling and read leveling in the controller. The board design has to support that compensation by keeping the stub from the main trace to each device short and consistent, and by keeping the trace impedance controlled along the whole chain.

The data nets are different again. Each byte lane, eight data lines plus the data strobe, is point to point or a two device topology, and the requirement is to match the lengths inside the lane to each other and to the strobe, rather than to match the lanes to one another. Treating the data and the address groups as one bus is a common and expensive mistake. Our notes on PCB design and layout cover the routing practices in more detail.

Length Matching and Skew

The matching budget follows from the unit interval. At 3200 megatransfers per second the interval is a little over three hundred picoseconds, and the propagation delay on a board is roughly six to seven picoseconds per millimetre. A mismatch of ten millimetres is therefore around sixty picoseconds, which is a fifth of the timing window, and that is before the effects of the vias, the connectors and the packages are counted.

The practical rules are to match within each byte lane including the strobe, to match the address, command and control group to a looser tolerance that the write leveling can absorb, and to keep the intra pair skew of a differential strobe very small. The clock is the reference for the address group and should be matched against it. Vias add delay and capacitance, so a net that changes layer should have the same number of layer changes as the nets it is matched against.

Impedance and Crosstalk

Single ended nets are usually routed at forty to fifty ohms to the reference plane, and differential strobes at eighty to one hundred ohms differential for DDR3 and lower for DDR4, following the controller’s specification rather than a general rule. The impedance only holds if the reference plane is continuous, so a layer change needs a return via close to the signal via and the plane must not be split under the bus.

Crosstalk is the other limiting effect, and it is controlled by spacing. A separation of three times the trace width between parallel runs, a short parallel length and a reference plane between the layers reduces the coupling. The worst case is usually between the data lines of adjacent byte lanes, or between the data and the strobe, and those pairs deserve the most separation and the shortest possible parallel run.

Power Integrity

The memory bus draws current in bursts, and the supply has to deliver it without moving. Each supply pin needs its own decoupling capacitor placed as close to the pin as the layout allows, with the capacitor land connected to the plane with short, wide links and to the device with a short via. The bulk capacitance sits elsewhere and handles the slower current changes.

On DDR3, the termination rail needs its own regulator that can source and sink current, because the termination absorbs energy when the line is high and returns it when the line is low. On DDR4, the on-die termination removes that rail but the 2.5 volt array supply takes its place, and its decoupling and its sequencing are just as important. The VPP supply is often overlooked until the first prototype behaves unpredictably.

The reference voltage, where the board still provides one, is a quiet analogue node. It should be generated from a stable divider, decoupled with a small capacitor and a large one, and routed away from the switching supplies and from the data lines.

Layer Count and Stack-Up

DDR3 can be routed on a four layer board at lower speeds if the bus is short and the routing is disciplined, but six layers is the practical minimum for a comfortable design and for anything above the middle of the speed range. DDR4 generally needs six layers, and a high speed or a wide bus design moves to eight or more, because the bus needs its own reference plane, the power distribution needs its own layer and the routing needs room to keep the groups apart.

The stack should be chosen so that every signal layer has an adjacent ground plane, the power distribution has a low impedance path and the layer transitions on the bus are few. A symmetrical stack keeps the board flat through assembly. Our notes on PCB manufacturing describe how the stack and the impedance control are produced.

Verification

A memory bus should be simulated before it is built, using the controller and device models and the actual stack, and it should be measured after it is built, with the eye diagram at the device pins and the timing margin at the extremes of the supply and the temperature range.

The functional test on a production board has to run a memory stress pattern at the full rate and at the temperature extremes, because a marginal bus passes at room temperature and fails in the field. Our notes on PCBA testing describe how these checks are structured, and our notes on quality management cover the process control that keeps the impedance within tolerance from board to board.

What Drives the Cost

The layer count is the first cost item, because the bus usually forces the design to six or eight layers. The impedance control, the tighter tolerances and the additional simulation and test time add cost, and a DDR4 design that needs a low loss laminate at the highest rates adds a material premium on top.

The saving available is in the design, not in the material. A well planned stack, a disciplined group routing and a short bus avoid an extra layer and avoid the respin that a marginal design produces. Our notes on PCB assembly group handles the assembly of these boards.

FAQ

What is the main layout difference between DDR3 and DDR4? The topology. DDR3 at higher speeds and DDR4 use fly-by routing with write and read leveling, while lower speed DDR3 can use a T-branch. The termination scheme and the supply rails also differ.

Does DDR4 need a VTT termination rail? No. The termination is on the die. DDR4 does need a separate 2.5 volt array supply, which has its own decoupling and sequencing requirements.

How many layers does a DDR4 board need? Six layers is the practical minimum, and eight or more is common for a wide or high speed bus where the groups need separation and the power distribution needs its own plane.

Why match lengths within a byte lane rather than across the whole bus? Because the byte lane and its strobe are sampled together, while the address group is compensated by write leveling and can tolerate a looser match.

Can a DDR bus be laid out without simulation? It can at low speed and short length, but at DDR4 rates the trace, the via and the package effects together consume most of the timing budget, so a simulation and a measurement are the cheaper path.

Conclusion

DDR3 and DDR4 share a purpose and differ in the details that decide whether the bus works. DDR4 runs faster and at a lower voltage, moves the termination onto the die and expects a fly-by topology with leveling, which changes the routing rules and the power design. Plan the stack around the bus, keep each group separate, match within the byte lanes, keep the reference planes continuous and verify with a simulation and a measurement rather than with a hope.