EMC Design Rules for High-Speed PCB Layout

EMC problems are almost never solved by a component added at the end of a project. They are avoided by decisions taken at the start of the layout, when the placement, the stack-up and the routing of the critical nets are still open. Once those are fixed, the options narrow to filtering, shielding and retries, and all three cost more than the original decision.

Two Mechanisms, Two Frequency Ranges

An EMC design has to deal with two mechanisms that behave differently and that are separated, roughly, by 30 MHz.

Above that frequency the dominant mechanism is radiation. Energy leaves the board through the fields around a current loop, and the amount that escapes depends on the area of the loop and on the frequency. This is the mechanism that most engineers think of first, because it is the one the EMC laboratory measures as radiated emissions.

Below that frequency the dominant mechanism is conduction. Energy travels out of the product along the cables that connect it, and it returns along the same cables to disturb the circuits inside. This is conducted emissions, and it is measured on the cable rather than in the air. Ignoring it because the frequencies are low is a common mistake, because the cables are the longest conductors in the system and they are efficient at carrying the disturbance out of the enclosure.

The two ranges therefore need two different treatments, and a product usually has to pass limits in both. It also follows that a design review that only considers the fast signals has only covered half of the subject.

Placement Decides Most of the Result

The layout step with the greatest influence on the final result is the placement of the devices, and the decisions are simple enough to apply as rules.

Keep the clock source and any other periodic generator away from the connectors, and especially away from cables that leave the enclosure. A clock beside an I/O connector couples into the harness, and the harness then radiates; moving the clock a few centimetres inward can remove several decibels from the measurement.

Keep the switching nodes short. The node in a switching regulator or a clock driver is the point of highest dV/dt on the board, and every millimetre of copper attached to it is a radiating element. Place the components so that the loop that carries the switching current is as small as the layout allows, and keep the sensitive circuitry away from it.

Group the circuits by function, with the noisy input protection and the interface drivers at the board edge and the sensitive analog or radio sections inside. This is the same placement discipline that a mixed-signal board needs, and it makes the filtering arrangements shorter and more effective.

Stack-Up and Critical Routing

Route the fast signals on inner layers wherever the stack allows. An inner trace is separated from the outside world by the surrounding material and, more importantly, it can be placed directly against a reference plane, which makes its return path predictable. A surface trace has a reference plane below it but is exposed above, so it radiates more for the same current.

The critical nets need a reference plane and an impedance target, and the reference has to be continuous along the whole route. A trace that changes reference planes, or that crosses a gap, produces the largest discontinuity in the design because the return current has to find another route. Where a layer change is unavoidable, the return path should be stitched with a via beside the signal via, so the current transfers to the new reference plane at the same point.

The same routing discipline controls reflections, and reflections matter for EMC because a reflected edge produces extra transitions and extra high-frequency energy. Matching the trace impedance to the driver and the load is a signal integrity measure, but it is also an emission measure, and the two benefits arrive together.

Loop Area and Return Path

The single most useful geometric idea in EMC is that of the loop area. Every current that flows out along one path returns along another, and the region enclosed by the two paths is the antenna. Reducing the area of that region reduces the radiated field directly, which is why a plane is so effective: the return current flows in the copper directly beneath the trace, and the loop collapses to almost nothing.

The related quantity is the loop impedance. A large loop has a high impedance, so a given current produces a larger voltage disturbance in the circuit as well as a larger radiated field. That is the reason a poorly planned return path degrades the circuit function at the same time as it increases emissions; the two effects come from the same geometry.

Where a noisy circuit cannot be contained by placement alone, splitting the ground plane to restrict the noise to a region is a legitimate technique, provided that no signal crosses the split without a defined return path. A split that is not accompanied by that rule moves the problem rather than solving it.

Slowing Down the Edges

The energy that radiates comes from the edge, not from the logic level, so anything that lengthens the edge reduces the emission. The options are a driver with a controlled output slew rate, a series resistor that limits the drive current, or a ferrite bead in series with the line. All three trade some timing margin for a reduction in the high-frequency content, and all three are cheap when they are designed in and awkward when they are added on a prototype.

Decoupling belongs in the same category. A capacitor only lowers the supply impedance over the range where it behaves capacitively, and above its self-resonance it behaves inductively and can make the impedance worse. Selecting the capacitor population by frequency response rather than by nominal value is what actually reduces the noise on the plane, and the plane noise is one of the paths by which switching energy reaches the outside.

Interface and Chassis Ground

The point where the board connects to the chassis is the boundary at which conducted emissions are dealt with. Filtering on the interface lines, placed close to the connector and referenced to the chassis rather than to the signal ground, removes the common-mode current before it leaves the board. The choice of a chassis ground connection, and the number of points at which the ground plane is tied to it, is a decision that belongs with the mechanical design and the EMC test plan rather than being left to the last review.

None of these measures can be verified on paper, but they can be reviewed, and the review is far cheaper than a test failure. Our design and layout review covers the placement, the stack-up and the return path structure before the data is released, and the stack-up options that make plane-referenced routing possible are listed on our PCB capabilities page. For boards that go to test as a complete assembly, the EMC-relevant construction details such as the chassis bond and the cable screening are documented with the build so that a production unit matches the tested prototype, which is part of our quality management flow.

FAQ

Should emissions below 30 MHz be ignored? No. That range is where conducted emissions live, and cables carry them outside the product even when the board itself is quiet.

Is it worth routing a fast signal on an inner layer? Yes, when the layer has a reference plane beneath it. The plane collapses the return loop and the surrounding material reduces the field that escapes.

Can a ground split contain a noisy circuit? It can restrict the noise to a region, but only if no signal crosses the split without a return path defined beside it.