Why Via Structure Is the Central HDI Decision

Once a design enters build-up technology, the way microvias are arranged decides almost everything downstream: how much routing area remains, how many sequential laminations are required, how reliably the board survives thermal cycling and how much yield the factory can achieve. Three arrangements dominate practice, and they are frequently confused with one another.

A staggered via places each microvia directly over the pad of the layer below but offset laterally from the via beneath, so the connection walks across the layers rather than forming a vertical column. A stacked via places microvias directly on top of one another, creating a continuous vertical connection through several build-up layers. A via-in-pad places the microvia inside the component land itself, usually filled and plated flat so the component can be mounted over it.

Each of these solves a different problem, and each carries a different manufacturing cost. The mistake is to treat them as interchangeable options on a checklist, because the choice interacts with routing density, signal integrity, thermal performance and assembly yield at the same time.

Staggered Vias: The Lower-Risk Default

Staggered construction is the most forgiving of the three. Because each via lands on a pad rather than on the filled via beneath, the process does not require perfect planarisation, and the registration tolerance is wider. Reliability is generally better under thermal cycling, because the connection path distributes stress instead of concentrating it in a single vertical column.

The cost is routing area. A staggered connection consumes lateral space on intermediate layers, which is exactly the resource that build-up technology was adopted to conserve. On a dense escape from a fine-pitch package, staggering can require more build-up layers than stacking would, which increases sequential lamination count and therefore cost.

For many designs the trade is still favourable. Where routing density is moderate and layer count is not the binding constraint, staggered vias give a robust board at a lower process risk, and the manufacturable yield is often better than a stacked design that is at the edge of the factory’s capability.

X-ray inspection helps but does not fully resolve the problem. A filled via with a small internal void may pass X-ray examination and still fail after thermal cycling, because the void becomes a stress concentration. The more reliable approach is process control on the fill itself, with periodic destructive cross-section samples confirming that the fill quality matches the assumption.

Stacked Vias: Density at a Cost

Stacking microvias directly creates a vertical interconnect that occupies almost no lateral area, freeing layers for routing. In designs where a high ball count device must escape to inner layers, this can be the only practical way to achieve the required density within a given layer count, making stacked vias an enabler rather than an optimisation.

The manufacturing requirements are severe. Each via must be filled and plated flat enough that the next build-up layer can be imaged on a planar surface, and each subsequent laser step must land precisely on the filled via below. Any void in the fill, any copper recession or any registration error propagates upward through the stack and can produce an open circuit that only electrical test will reveal.

Reliability is also more demanding. A continuous column of plated copper through several dielectric layers experiences more stress under thermal cycling than a staggered path, because the expansion of the surrounding resin acts along the entire column. Designs that use stacked vias in thermally aggressive applications should be validated by thermal cycling, not only by electrical test.

Via-in-Pad: Making Room Under the Component

Via-in-pad places the connection inside the component land, which removes the need for a short trace between the pad and the via. On fine-pitch ball grid arrays this can be decisive, because the routing channels between pads are often too narrow to accommodate a via and a trace.

The technique requires the via to be filled and plated flat so that the component sits on a planar surface. Voiding in the fill will cause solder to wick into the via during reflow, producing an open or a weak joint. For that reason via-in-pad is normally coupled with a specific fill material and a defined process, and both must be qualified together rather than assumed to transfer between suppliers.

Thermal benefits often accompany the electrical ones, and they matter most on volume assemblies. A via-in-pad array beneath a power device acts as a thermal path into inner copper planes as well as an electrical connection, and the same array that improves grounding also improves heat spreading. That dual function is why via-in-pad is standard practice under high-power components in dense assemblies.

How the Choices Interact With Materials and Process

The three structures do not exist independently of the materials. Build-up dielectric has to flow around the copper features and fill the spaces between vias, and its behaviour during lamination depends on the pattern of those features. A region with dense stacked vias behaves differently from a region with sparse staggered ones, and both differ from a large copper plane.

This leads to the practical requirement for balanced copper distribution. Large variations in local copper density cause the resin to flow unevenly, producing thickness variation that changes impedance and can produce voids. Dense via clusters therefore create local design rules, and layout planning has to account for them rather than treating vias as free.

The plating process also links to the structure. Stacked and via-in-pad designs require reliable filling, which depends on the plating chemistry and the via geometry. A factory that can fill a 0.1 millimetre via may not be able to fill a larger one without voiding, because the filling mechanism depends on the aspect ratio. Specification should therefore be written in terms of what the process can actually achieve.

Reliability Differences That Show Up Late

The reliability consequences of a via structure rarely appear in functional test. They appear after thermal cycling, after vibration exposure or after assembly reflow with its associated thermal shock. The mechanism is straightforward: the plated copper and the surrounding resin expand at different rates, and the interface between them accumulates damage with each cycle.

Staggered vias distribute that damage across a wider area, while stacked vias concentrate it. Via-in-pad adds a third consideration, because the solder joint above the filled via experiences its own cycling and the fill material’s behaviour influences how the joint deforms. These effects are difficult to model, which is why qualification by test remains the practical approach.

Customers building for automotive, industrial or infrastructure applications should expect their supplier to offer evidence from thermal cycling on a representative structure rather than a generic statement of compliance. A structure that works in a consumer product may not survive a fifteen-year industrial duty cycle, and the difference is not visible on a data sheet.

Matching the Structure to the Design Intent

A practical selection process begins with the bottleneck. If the constraint is escaping a dense device, via-in-pad or stacked vias address it directly. If the constraint is total layer count, stacking frees the most area. If the constraint is reliability in a harsh environment, staggering is usually the safer choice even at the cost of additional layers.

Mixed approaches are common and sensible. Many designs use via-in-pad under the processor, stacked vias in the densest escape region and staggered vias elsewhere on the same board. That mix is legitimate, but it has to be specified clearly, because each region imposes different process requirements on the fabricator.

Specifying the mix explicitly, with the reasoning documented, also makes the design review with the manufacturer far more productive. A fabricator who understands why the stacking exists can suggest alternatives when the yield data indicates a problem, instead of simply reporting rejects. That exchange is one of the strongest arguments for involving the manufacturing capability team during layout rather than after it.

Volume considerations should be stated as well. A structure that produces acceptable yield in a prototype batch of twenty panels may behave differently when a thousand panels run through the same line, because process drift accumulates over time rather than within a single build. Suppliers who track fill quality and registration as control chart parameters, not as inspection outcomes, are better able to detect that drift before it produces a rejected lot.

What to Specify Before Release

Before a design enters production, the via specification should state the structure type for each region, the required microvia diameter and aspect ratio, the fill requirement, and the reliability testing expected. It should also state the measurement method for via quality, since optical inspection of filled microvias is limited and cross-sectioning is destructive.

Equally important is the definition of acceptable fill. Void size limits, copper recession limits and surface planarity criteria should be expressed numerically. Leaving these to interpretation is the most common cause of disagreement between a designer who assumes a fully filled via and a factory that delivers a partially filled one.

Finally, the specification should record which features are critical to function and which are preferred. Manufacturers can often recover yield by relaxing a non-critical parameter, but only if they know which ones those are. That information, combined with a documented quality management process and a stable production process, is what allows an HDI programme to hold its yield as volume increases.