High Speed PCB Design for DDR, PCIe and USB 3.0
As product performance rises, high speed interfaces have moved from specialist designs into ordinary ones. A memory bus, a serial expansion link or a fast USB port appears on boards that would not have had one a few years ago, and a layout that ignores the requirements of those interfaces produces a product that runs at a reduced rate, loses data, or does not work at all. In high speed PCB design the work rests on three things that have to be considered together: the integrity of the signal, the matching of the timing, and the integrity of the supply.
The Interfaces Covered
Memory interfaces are designed across the range from DDR3 to DDR4, including the low power variants used in mobile products, with the address, command, data and clock groups length matched and the topology arranged to suit the controller. Serial expansion links at the third and fourth generation rates are designed with controlled differential impedance, the via stub treated, the coupling capacitors placed correctly and the link trained successfully.
Fast USB links, including the reversible connector, are designed as differential pairs at five and ten gigabits per second, with the connector handled as part of the channel and the protection placed so that it does not disturb the signal. Ethernet and other serialiser lanes, from gigabit to ten gigabit and optical interfaces, are designed with the return loss and the insertion loss in mind and the impedance kept continuous. Display and camera interfaces and storage interfaces such as SATA complete the set, each with its own requirements on the pairing, the length and the protection.
The Numbers Behind the Design
Serialiser rates above twenty five gigabits per second are supported. Differential impedance is held at one hundred ohms and single ended at fifty ohms, both with a tolerance of ten percent. Matching within a differential pair is held to five thousandths of an inch, and matching between groups follows the timing margin the controller allows rather than a fixed figure. Stack-ups from six to thirty layers are designed, with the impedance calculated rather than assumed, and simulation is available for the signal and the supply where the design warrants it. The applications include servers, communications equipment, industrial control, consumer products and medical devices.
Where the Difficulty Lies
Impedance continuity is the first requirement. A reflection at a discontinuity disturbs the signal, so the impedance is controlled from the stack-up onwards, the return path at a via is given a ground via so that the current is not forced to detour, the anti-pad is sized to suit, and the entry into a connector is examined as a region where the impedance changes. A trace that is correct along its length and wrong at its two ends behaves like a bad trace.
Length matching is the second. A parallel bus such as a memory interface requires the groups to be matched in a way that respects the timing the controller specifies, and the permitted difference is calculated from the actual stack-up rather than copied from a table. Margin is left deliberately, because the calculation is a model of the board and not the board itself.
Power integrity is the third, and it is the one that is most often underestimated. A high speed device draws a large current with a fast rate of change, and a supply network that was designed by placing capacitors where they fitted produces a voltage that moves. The plane arrangement, the placement of the decoupling, and the target impedance of the network are treated as a design problem in the same way as the signal routing.
Signal integrity is the fourth, and it is supported by the compatibility work: a signal layer adjacent to a reference plane, differential routing where the interface is differential, no crossing of a plane split, and filtering at the interfaces where the cable leaves the board.
Simulation and Production
For the fastest links, and for designs where the margin is thin, the critical nets are simulated before the board is made. The purpose is not to prove that the design works, which only the board can do, but to find the obvious problems while a change still costs nothing. A simulation report that shows the eye diagram of a link with adequate margin is also a useful document to hold if a later problem has to be investigated.
Because the same group fabricates and assembles, the choices made in the layout are checked against what the process can hold. The impedance calculation uses the factory’s own dielectric thickness and copper figures, which is what makes the number meaningful, and the board moves from fabrication into assembly without being packed and reopened in between.
What the Customer Supplies
The schematic, the device data with particular attention to the layout guidance the manufacturer publishes, the mechanical requirements and any specific performance requirement are the starting point, and a reference design or an evaluation board is a useful addition. Where the customer supplies nothing beyond the schematic, the design still proceeds, but the manufacturer’s guidance is what the high speed portion is built on.
A board of six to eight layers with a memory interface and a fast USB port normally takes seven to fifteen working days to lay out. A board of more than a dozen layers with several memory groups and several serial links takes three to four weeks with simulation included. Our PCB design and layout group does this work, the boards are produced by PCB manufacturing, and the records are held under quality management.
What Separates a Working Board From a Marginal One
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Most high speed designs that fail do not fail completely. They run at a reduced rate, they pass on the bench and fail in the field, or they work on one board and not on the next. The causes are usually the same few: a return path that was interrupted at a via or across a plane split, a pair that was separated around an obstacle and rejoined, a stub left on a via that is long enough to resonate at the frequency of interest, a decoupling arrangement that was placed by convenience, or a connector whose entry was not treated as part of the channel.
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None of those is a large change, and all of them are cheap to avoid while the layout is being drawn and expensive to correct afterwards. That is the argument for treating the high speed portion of a design as a planned exercise with a stack-up, a set of constraints and a review, rather than as the same routing as the rest of the board with a narrower width.
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A review at the end is worth having as well, because the person who routed the board knows where the difficult sections are and the person reviewing it does not, which is exactly the difference that finds the problem.
FAQ
Who supplies the design guidance? The device manufacturer publishes layout guidance for each high speed interface, and the design follows it, since it encodes the requirements the silicon was characterised against.
Is simulation always required? It is added for the fastest links and where the timing or impedance margin is thin, and it is optional for an interface with comfortable margin.
Can a high speed board be produced by the same group? Yes, and because the impedance calculation uses the factory’s process figures, the design and the board are more likely to agree.
