Impedance Control PCB: Structures, Tolerances and Testing

What Impedance Control Means in Practice

Impedance control is the discipline of making a trace behave as a transmission line of a defined characteristic impedance rather than as a wire. On a controlled impedance board, a signal trace of a given type presents 50 ohms, or 90 or 100 ohms differentially, consistently along its length and consistently from board to board.

The reason it matters is that an impedance mismatch reflects energy back toward the source. Those reflections do not disappear; they arrive at the receiver at the wrong time, they interfere with the signal itself, and they radiate. The visible consequences are timing jitter, a degraded eye diagram, and emissions that push a product over its EMC limit. None of that appears on a schematic, which is why impedance has to be treated as a manufacturing specification rather than a design note.

The applications are the ones carrying fast edges: DDR and PCI Express memory and interconnect, USB and HDMI, RF and microwave circuits, 5G equipment, and automotive and industrial control boards where the interface speeds have moved into the range where it matters.

The Underlying Principle

Characteristic impedance is the ratio of voltage to current for a wave travelling along the line, and it is determined by the geometry of the conductor and the electrical properties of the dielectric around it. It is not a property of the copper alone, and it is not fixed by the trace width alone.

The practical rule for when this matters is a length threshold rather than a frequency threshold. When the trace length exceeds roughly one sixth of the propagation distance corresponding to the signal’s rise time, the trace has to be treated as a transmission line. That is why a slow signal on a long trace can need impedance control while a fast signal on a very short trace may not.

A stable impedance reduces reflection and radiated emission at the same time, which is why impedance control appears in both signal integrity and EMC discussions. They are the same problem seen from different directions.

Transmission Line Structures

• Microstrip: the trace sits on an outer layer with a reference plane below. Simple to fabricate, but exposed to the environment and to coupling from adjacent structures.
• Stripline: the trace is buried between two reference planes. Better impedance stability and better EMI behaviour, which is why high layer count high speed boards favour it.
• Coplanar waveguide: a trace with ground on both sides on the same layer, often used in RF work for tighter impedance control and reduced dispersion.
• Single ended against differential: single ended impedance is typically 50 ohms; differential pairs are commonly 90 or 100 ohms, defined by the pair geometry and the coupling between the two traces.

The differential case is worth a note because it is frequently misunderstood. Differential impedance is not twice the single ended impedance of one trace; it depends on the spacing between the pair and the presence of the reference plane. Changing the gap to save routing space changes the impedance, which is why the gap has to be treated as a controlled parameter rather than a layout convenience.

What Determines the Manufactured Impedance

• Trace width and copper thickness: wider traces and thicker copper give lower impedance.
• Dielectric constant and loss factor: the laminate properties, which is the main reason high speed designs move away from standard FR-4.
• Dielectric thickness: the separation between the trace and its reference plane, and one of the most influential parameters.
• Reference plane integrity: a continuous, unbroken plane. A split under a trace changes the impedance and the return path simultaneously.

Of these, dielectric thickness and reference continuity are the ones most often compromised. Thickness is a lamination outcome, and reference continuity is a layout outcome, and both are easy to lose while solving an unrelated problem.

Stackup Design

• Four and six layer boards are the common baseline for impedance controlled work, and cover a large proportion of designs.
• Eight layers and above typically use buried stripline structures for the high speed signals, since the additional planes make it possible to reference both sides of a trace.
• Symmetry: a stackup balanced about the centre line warps less and holds its dielectric dimensions better through lamination.
• Manufacturability: the stackup has to be one the fabricator can actually build to the required tolerance, which is a conversation to have before the routing is finalised rather than after.

This is where the design and the process meet, and it is the reason stackup design belongs in the layout phase with the fabricator involved. A stackup chosen for electrical convenience that the process cannot hold to tolerance produces a board whose measured impedance does not match the simulation.

Tolerance Grades

• Standard tolerance of about plus or minus ten percent: the normal requirement, and adequate for many high speed interfaces.
• High precision at plus or minus five percent: used where the signal integrity margin is thin, and commonly required on RF and on high speed differential links.
• Plus or minus three percent and tighter: achievable on specific structures after an engineering assessment, and only justified where the design genuinely cannot tolerate more.

The reason tighter tolerance costs more is straightforward. A five percent window means the process has to hold the trace width, the dielectric thickness and the copper thickness within correspondingly tighter ranges, and the yield falls when the window narrows. The recognised performance and design standards provide the reference framework, but the tolerance number is a commercial decision and it should be chosen from the design margin rather than by default. Not every high speed net needs the tightest grade available.

Calculation and Simulation

Impedance can be estimated with closed form formulas, but a field solver is what reflects real manufacturing conditions, including the effects of the solder mask, the copper surface roughness and the actual structure geometry. Design tools such as the standard two dimensional field solvers used for stackup design are the normal starting point, and the resulting stackup is then confirmed with the fabricator against the material they will actually use.

The output of that work is a stackup drawing and an impedance table: the target impedance, the layer, the structure type and the trace geometry for each net class. That table is what the fabricator builds to, and it is the document that makes the requirement unambiguous.

How It Is Achieved in Manufacturing

• Adjusting trace width and dielectric thickness to reach the target, based on the actual material properties rather than the datasheet nominal values.
• Etch compensation: the etching process removes copper from the trace sidewall as well as from the top, so the finished width is narrower than the artwork. Compensation for that effect is one of the main sources of impedance error when it is not handled.
• Lamination precision and material consistency: the dielectric thickness after pressing is what determines the impedance, and it varies with the material, the press profile and the panel.

Because all three are process outcomes, the verification is a measurement rather than an assumption. That is the role of coupon based TDR impedance testing, which is the mainstream method for verifying the manufactured impedance on the production panel.

Testing and Verification

• TDR testing is the standard method, and the primary means of confirming that the manufactured board matches the specified impedance.
• Coupons are built on the production panel with the same process and the same structures as the functional traces, which is what makes the measurement representative.
• Reports provide the measured values against the specified tolerance, forming the evidence that the board meets its specification.

Where the channel performance rather than the impedance itself is the acceptance criterion, the eye diagram provides the system level view, since it captures the combined effect of impedance, loss, crosstalk and any stub or discontinuity in the path.

Common Problems

• Over etching or under etching shifting the trace width and with it the impedance. A small dimensional change moves the impedance more than most designers expect.
• Material batch variation: dielectric constant varies slightly between laminate batches, which shifts the impedance even when the geometry is identical.
• Incomplete stackup information in the fabrication package, which is the most common cause of a failure. If the requirement is not stated with the target value, the structure type and the tolerance, the fabricator has to guess.
• A discontinuous reference plane, which is a design error rather than a manufacturing one but produces the same result.

Cost

Cost scales with the tolerance and the material rather than with the circuit. As planning reference figures, a standard board runs roughly 0.05 to 0.12 dollars per square inch, an impedance controlled board at plus or minus ten percent roughly 0.12 to 0.25 dollars per square inch, and a high precision board at plus or minus five percent roughly 0.20 to 0.40 dollars per square inch. The main drivers are the tolerance grade, the material class, and the testing and documentation requirements.

The practical guidance is to apply the strictest tolerance only where the design needs it. A board can carry several impedance classes, with the sensitive differential pairs held to the tighter specification while the general high speed nets use the standard grade. That approach captures most of the benefit at a controlled cost.

Specifying the Requirement

What the fabrication package needs to contain is short and specific.

• The target impedance value for each net class.
• The impedance type, single ended or differential, and the reference layer for each.
• The tolerance grade required, as a percentage.
• A stackup drawing and impedance table, which removes most of the ambiguity and the risk of rework.

The most frequent mistake is leaving the reference layer undefined. A trace that changes reference layer through a via, or that runs across a plane split, does not have the impedance the table claims, and no amount of manufacturing precision fixes that. The engineering work belongs in the fabrication review with that information complete.

Selecting a Manufacturer

• Demonstrated impedance control capability, including high layer count and high speed constructions.
• TDR testing and reporting, with documented process confirmation rather than a verbal assurance.
• Material processing experience with the laminate family the design uses.
• Engineering input on stackup, so that the design is matched to a construction the process can hold.

Lead times for impedance controlled work typically run five to seven working days for prototypes and seven to ten working days for small batches.

Frequently Asked Questions

What is a controlled impedance PCB? A board where the trace geometry, dielectric material and stackup are specified and controlled so that the signal traces hold a defined characteristic impedance.

Which impedance values are common? 50 ohms single ended, and 90 or 100 ohms differential.

How accurately can impedance be controlled in production? Plus or minus ten percent and plus or minus five percent are both achievable in volume. Tighter than five percent requires an engineering assessment and a specific structure.

How is it verified? By TDR measurement on coupons that are built on the production panel with the same process as the functional traces.

Summary

Impedance control is the practice of making traces behave as transmission lines of a defined characteristic impedance, and it becomes necessary when the trace length exceeds roughly a sixth of the propagation distance for the signal’s rise time. Above that threshold, an impedance mismatch produces reflection, jitter, a degraded eye and unwanted emissions.

The impedance is set by trace width and copper thickness, the dielectric constant and thickness, and the integrity of the reference plane, in the structure chosen: microstrip, stripline or coplanar waveguide, in single ended or differential form. Because three of those four are manufacturing outcomes, the specification only has meaning when it is written as a measurable target with a stackup drawing and an impedance table, and confirmed by TDR measurement on production coupons.

The cost scales with the tolerance grade and the material rather than with the circuit complexity, which makes the engineering decision straightforward.