Impedance Control Verification: TDR Coupons and Trace Width

A board can be etched perfectly and still fail its impedance control requirement, because impedance is set by the dielectric thickness and the dielectric constant as much as by the trace width. Verification therefore belongs on a coupon that shares the production stack-up, measured with a time domain reflectometer before the panels are assembled.

Why Impedance Is Verified on the Coupon

A finished board cannot be probed cleanly. Components, mask and finish all sit between the probe and the trace, so a measurement taken on a routed trace includes the effects of everything around it. A coupon built on the same panel, with the same stack-up, plating and finish, isolates the transmission line and gives a number that can be compared across lots.

The coupon should be placed where its environment matches the product as closely as possible: same copper density, same distance to the panel edge, same plane construction. A coupon in a bare corner of the panel with no adjacent copper measures a different characteristic impedance from a trace running through a dense area.

Coupon Design and Reference Planes

A usable coupon carries the whole family of line types used on the product: single-ended traces at each target impedance, differential pairs, and where relevant a coplanar structure. Each line is 100 to 150 mm long, long enough that the reflection from the far end separates from the launch discontinuity on the TDR display, and each terminates in a launch pattern the probe can reach.

The reference plane under the coupon must be continuous. A plane split or a stitching via placed under the launch adds a discontinuity that appears on the trace as a blip, and it is easy to mistake that blip for a width error. Coupons should also carry a dielectric thickness measurement structure so the electrical result can be checked against the physical stack-up.

TDR Setup: Rise Time, Launch and Calibration

TDR resolution is set by the step rise time. A 35 ps step resolves features down to a few millimetres and is the usual choice for board coupons; a much slower step smears the launch discontinuity into the trace and hides short sections of incorrect width. The sampling head should have at least three times the bandwidth implied by the rise time to avoid adding its own distortion.

Calibrate with a known air line or a precision standard so the reference plane is set at the probe tip, then verify that a 50 ohm standard reads within 1 ohm. Launch quality dominates the result: a probe that makes poor ground contact adds inductance at the start of the trace and produces a rising impedance curve that has nothing to do with the board.

Reading the Trace: Z0, Reflections and Length

Read the flat portion of the trace, not the value at the launch. A correctly designed measurement shows a short discontinuity at the connector, then a flat plateau, then another discontinuity at the far end. Take the mean over the middle 50 percent of the length so a small amount of ripple does not bias the result.

Reflections are diagnostics rather than noise. A localized dip means the dielectric is thin there or the trace is wide; a hump means the opposite. A gradual slope along the whole line points to a thickness gradient across the panel, which is a pressing or plating issue rather than an etching one.

Trace Width and Dielectric Tolerance Budget

Impedance tolerances of plus or minus 10 percent are routine, plus or minus 5 percent is achievable, and the budget has to be allocated before the board is made. Trace width typically contributes 3 to 5 percent of impedance variation, dielectric thickness 5 to 8 percent, and dielectric constant 2 to 3 percent, which means width alone cannot absorb the whole allowance.

Because the contributors are independent, a shop that holds width tightly but not thickness will still miss. The drawing should state the target impedance, the measurement method, and the stack-up tolerance that supports it, so the two sides of the tolerance are consistent. Where the product needs 5 percent, the stack-up has to be specified with a controlled dielectric, not a generic FR-4 range.

Differential Pairs and Intra-Pair Skew

Differential impedance of 100 ohms is set by the width, the gap and the distance to the plane, and the gap is the hardest of the three to hold on a dense layer. Coupled lines also have to be measured with both conductors driven, because measuring one side against the other produces a number that does not represent the pair.

Intra-pair skew is a timing property rather than an impedance one, and it is usually limited to a few picoseconds, which corresponds to a length difference of well under a millimetre. The coupon should include a pair with the same length-matching rules as the product, and the measurement should report skew separately from impedance so the two can be diagnosed independently.

<img src="https://www.gopcba.com/wp-content/uploads/2026/05/Solar-Inverter-System-PCBA.jpg" alt="Time domain reflectometer trace showing 50 ohm characteristic impedance” />

Solder Mask, Copper Roughness and Finish Effects

Mask over a trace lowers impedance slightly by adding a dielectric layer with a higher constant than air, typically a few ohms on a 50 ohm line. Copper roughness raises the effective resistance and changes the delay slightly, and it becomes visible only at high frequencies. Both effects should be measured rather than assumed, because they scale differently with line geometry.

Most coupons are measured at the same point in the process as the product, either before or after mask and finish, and the drawing has to say which. Comparing a pre-mask coupon against a post-mask specification is a common source of apparent nonconformance that costs a lot of time to unravel.

Accept and Reject Criteria and Sampling

State the acceptance window, the number of coupons measured per panel or per lot, and whether the value is compared to the drawing target or to the measured coupon average. Where the coupon and product share the same cross-section, a per-lot sample gives good confidence; where the product uses a different line geometry, each panel may need its own coupon.

Also decide in advance what happens when a coupon is out but a failure analysis shows the product is electrically acceptable. Having a documented route for engineering concession prevents a situation where panels sit quarantined for days while the decision is argued case by case.

When a Panel Fails: Rework or Reject

Impedance cannot be reworked on a finished panel. If the coupon is out and the deviation traces to the laminate, the panel is scrap; if it traces to a plating or pressing condition, the fix is upstream and the affected panels are still scrap. The value of measurement is the feedback it gives to the fabrication process, not an option to repair the unit in hand.

That makes the trend more useful than the individual reading. A coupon at the edge of the window on three consecutive lots predicts a failing lot, and the correction is cheaper when it is applied to the process rather than to the panels. Record every result against the panel serial so a drift can be seen before it becomes a rejection.

Related reading: our fabrication notes, board quality and design release notes cover the same ground.

FAQ

Can impedance be measured on a finished board? Not reliably. Components, mask and finish distort the measurement, so the verified structure is a coupon that shares the production stack-up and finish.

What rise time should a TDR use for PCB coupons? Roughly 35 ps, which resolves short discontinuities without adding its own smear. The sampling head needs at least about three times the bandwidth implied by that step.

How much of the tolerance does trace width contribute? Typically 3 to 5 percent of the impedance budget, while dielectric thickness contributes 5 to 8 percent. Width alone cannot hold a 5 percent specification.