Impedance Discontinuity in PCB Manufacturing: Causes and Fixes

What an Impedance Discontinuity Really Is

Every high speed net carries a target impedance: 50 or 75 ohm single ended for most RF and clock nets, 90 ohm for USB, 100 ohm for PCIe, HDMI and differential pairs, 120 ohm for some twisted pair style links. The number only works if it stays constant along the whole path. Any point where the cross section, the return path or the material changes creates a local impedance that differs from the rest of the trace, and the energy that arrives there splits: part continues, part reflects back toward the driver.

The result is not a clean failure. It is ringing, overshoot, jitter and a smaller eye opening, all of which eat margin that the rest of the design already spent. On a PCIe or DDR interface those symptoms show up as intermittent link errors rather than a dead board, which makes them expensive to find in the field.

The Main Sources in Manufacturing

A discontinuity can be designed in, or it can be created in the shop. Both end up on the same curve.

• Trace width drift. Etching tolerance, copper thickness variation and plating thickness all shift the finished width. A ten percent width change on a microstrip moves the impedance by roughly five percent.
• Dielectric constant variation. Resin content differs between laminate batches and between the warp and fill directions. A Dk shift of 0.2 on a 100 micron dielectric is enough to move a 50 ohm line off target.
• Layer spacing. Press pressure and prepreg flow decide the finished dielectric height. Uneven spacing across a panel changes impedance from one area to another.
• Via structures. The barrel, the pad, the antipad and any leftover stub all behave as a small capacitive or inductive section in the middle of a matched line.
• Connectors and packages. The pad at the connector footprint is wider than the trace, and the fields fringing around it lower the local impedance.
• Solder mask and finish. Mask over a microstrip pulls the effective Dk up slightly. Thin gold or ENIG layers matter less, but thick soldermask over a tightly spaced line can be worth a few ohms.

None of these are exotic. They are the ordinary spread of a production process, which is why PCB manufacturing control and a stackup agreed with the fabricator matter more than the last decimal of an impedance calculator.

Vias Are the Usual Suspect

On most boards the via dominates the reflection budget. A through via that connects a signal from the top layer to an inner layer keeps its full barrel, and everything below the connection point is a stub: an unterminated transmission line hanging off the net. At 10 GHz a 2 mm stub is long enough to notch the channel response badly.

Three standard answers exist. Back drilling removes the stub with a controlled depth drill after plating. Blind and buried vias build the connection only through the layers needed, which keeps the stub short or eliminates it. Ground vias placed next to the signal via give the returning current a short path and keep the local impedance closer to the trace value. On dense HDI work with microvias, the stub problem mostly disappears but the pad capacitance of stacked microvias becomes the new item to watch, as covered in HDI PCB design.

How the Reflection Shows Up

At the far end of a lossy channel the damages add up rather than cancel. Reflected energy arrives back at the driver, is re reflected, and appears as post cursor noise at the receiver. The practical symptoms are a slower edge, a jitter histogram that spreads on both sides, an eye diagram that closes from the top, and a bit error rate that climbs faster with temperature than the link budget predicted.

In a spreadsheet this looks like degraded margin. On a scope it looks like ringing on the first nanosecond of every transition. Both point back to the same geometry problem, which is why it pays to look at the physical structure before blaming the SerDes settings.

Finding the Discontinuity

Time domain reflectometry is the standard tool. A fast pulse is launched into the trace and the reflected voltage is plotted against time; because time maps to distance through the effective propagation velocity, a bump on the curve locates the impedance step within a few millimetres. The technique, its resolution limits and how coupons are written are described in TDR impedance testing.

Other tools answer different questions. A vector network analyser measures return loss and insertion loss across frequency and is the better choice above 10 GHz. Full channel simulation in a field solver or a signal integrity tool lets the designer sweep via stub length, antipad diameter and pad geometry before the board is even routed. Coupons on the production panel then confirm that the shipped stackup matches the model.

For a quick sanity check at the bench, a step from a clock source plus a fast scope probe often shows the reflection plainly enough to identify which structure is responsible.

Design Rules That Keep the Line Uniform

Most discontinuities are cheaper to prevent than to repair.

• Keep one cross section per net class. If a trace must change width, change it in short tapered steps instead of a single abrupt neck down.
• Keep a solid reference plane under every high speed trace. A slot or a plane split forces the return current to detour, which raises inductance and looks exactly like a series discontinuity.
• Budget the via count per net and place a ground via within a millimetre of every signal via used above about 5 GHz.
• Route differential pairs with constant spacing. Necking the pair apart to clear a via is the most common cause of a common mode bump.
• Terminate at the connector with a transition pad that tapers from the connector land to the trace width, rather than stepping straight.
• Agree the stackup, the target impedance and the finished copper weight with the fabricator before routing, and ask for the impedance coupon data in the first article report.

Working With the Fabricator

Impedance control is a joint activity, not a specification handed over at the end. A useful conversation covers three things before the Gerbers are sent: which nets are controlled and at what value, what tolerance is acceptable, and how the coupon will be measured. Typical practice is plus or minus ten percent for ordinary controlled impedance, plus or minus five percent for tight high speed work, and tighter still for RF.

Once the design is fixed, the fabricator adjusts line width and sometimes dielectric thickness against the measured panel to land on target. That is why the same Gerber file can produce slightly different measured impedance at two suppliers: the laminate batches, the plating thickness and the etch compensation differ. Keeping the stackup stable between builds removes one variable from the link budget.

When a design is close to the edge, the practical fix list is short: shorten or back drill the stubs, add return vias, smooth the necks, and confirm the measurement on the coupon rather than on the assembled board. Where the layout itself is the limiting factor, revisiting the layer assignment through PCB design and layout usually recovers more margin than any component change.

FAQ

Does a small impedance bump matter at 1 GHz? Rarely on its own. Many small bumps along one net do matter, because their reflections accumulate.

Can impedance be fixed after the board is made? Not on the board itself. You can adjust the rework, add discrete damping, or reduce the data rate, but the geometry fix belongs in the next revision.

Is an impedance coupon enough proof? It proves the process. It does not prove the routed geometry, which is why simulation and, for critical links, a measured PCB eye diagram on a real assembly still add value.

Which is worse, a capacitive or an inductive step? Both hurt. A wide pad produces a capacitive dip that slows the edge; a long stub or a narrow neck is inductive and adds ringing.

Summary

Impedance discontinuity is the gap between the impedance a design predicts and the impedance a board actually presents. It comes from width and Dk drift, from uneven dielectric spacing, from vias, pads and connectors, and it shows up as reflection, jitter and a closed eye. The control levers are straightforward: agree the stackup early, keep one cross section per net class, keep the return path solid, shorten or back drill the stubs, and verify with a coupon and a measurement instead of trusting the calculator alone.