Light Load Ripple: When the DCDC Switches Into PFM Mode

A power board that produces a tidy waveform under load suddenly shows bursts of switching followed by quiet intervals, and the output ripple grows in amplitude and drops in frequency. The usual reaction is to suspect the compensation, replace the regulator, or add output capacitance. On a converter that supports more than one light load strategy, the same observation may simply be the controller doing what it was designed to do.

The controller has traded waveform regularity for lower switching loss. Understanding which modulation mode is active is the first step of the investigation, and skipping it sends every later change in the wrong direction.

What PWM and PFM Actually Regulate

In PWM the switching period stays essentially constant and the controller adjusts the on time, or the duty relationship, to move the energy it needs. The fixed rhythm makes the spectrum predictable and simplifies filtering and synchronisation.

In PFM mode the controller instead adjusts how often pulses appear. The on time may be roughly constant while the interval between groups of pulses varies with the load. Real devices implement this under several names, including pulse skipping and burst modes, and the exact behaviour differs between parts. The datasheet of the specific device is the only reliable description of when the mode is entered, how the threshold is set, and what the waveform looks like.

Why a Controller Chooses to Switch Less

Every switching event costs gate drive energy, capacitor charge and discharge, and device transition loss. Under heavy load those costs are small compared with the power being delivered. Under light load the same fixed costs become a large fraction of the total, and the efficiency curve of a converter running continuously will fall away as the load disappears.

The alternative is to deliver a group of pulses, raise the output towards its target, then stop switching until the output has sagged to an internal threshold. Efficiency improves, but the ripple becomes lower in frequency and the spectrum is no longer concentrated at a single switching frequency. That change is a deliberate trade against emissions and ripple rather than a fault.

Telling a Mode Change From an Unstable Loop

Look at the switch node first. A mode change produces grouped pulses separated by stable quiet intervals; an unstable loop usually produces irregular jitter without a stable silent period. Then look at the load: confirm that the change coincides with the load falling and that continuous switching returns when the load returns.

Check the control configuration next. A mode pin, a register bit or a default start-up setting may allow automatic entry into PFM or pulse skipping, and the board may be doing exactly what its configuration permits. Read the datasheet section on light load behaviour, forced PWM options and the typical waveforms rather than generalising from another part. Finally, confirm that the output stays within its specification: a mode change is allowed to alter the ripple shape, but it is not allowed to push the rail outside its steady state, transient or tolerance limits.

Is Forced PWM Better

Forced PWM keeps the switching frequency fixed, which is valuable when the spectrum has to be controlled: audio band noise, radio receive band interference and sampled data systems all benefit from a known switching frequency that can be filtered or avoided.

The price is light load efficiency. The converter keeps switching, the standby current rises, and a battery powered product pays for the predictability. Whether that is acceptable is a system decision about battery life, standby current, ripple, emissions, audible noise and synchronisation, and it should be made against those requirements rather than against the appearance of the waveform.

Working Through a Light Load Ripple Report

Repeat the measurement with a proper probe connection first, with the shortest possible ground loop, so that pickup is not mistaken for a high frequency spike. Observe the output and the switch node at the same time, and confirm whether the ripple change corresponds to a change in pulse rhythm. Record the input voltage, the output voltage and the load point so that the operating region where the behaviour occurs is defined rather than remembered.

Then confirm the mode control pins, the firmware configuration and the datasheet behaviour for the specific part. Only after the mode has been shown to be unexpected, or the output shown to be outside its specification, does it make sense to investigate the compensation network, the component values, the layout and the loop response. Investigating the loop first is the most common waste of a day in this class of problem, because the loop is often working correctly around a mode the engineer did not know was active.

Three Moves That Go Wrong

Adding output capacitance at the first sign of ripple changes the output network without necessarily changing the controller light load policy, and it can alter the transient response that was previously acceptable. Looking only at the output voltage and never at the switch node removes the information needed to distinguish a mode change from a control failure. Applying experience from a different part number is unreliable because the thresholds, the naming and the entry conditions for PFM, burst and pulse skipping differ between manufacturers and even between devices in the same family.

Where the Layout and the Components Fit In

Once the mode is understood, the physical design still decides how well the converter behaves inside it. The input loop from the input capacitor through the switches and back carries the highest current derivative in the design, and it should be as small as the layout permits. The switch node copper should be small rather than generous, because it is a radiating area, and the feedback divider should sense the output at the point the load sees rather than at the end of a long trace.

The components chosen also set the limits of what the mode can achieve. A low ESR output capacitor determines how far the output moves during a burst interval, and an inductor with a suitable saturation current keeps the pulses well behaved when the load steps up abruptly. Those are selections to review against the light load case as well as the full load case, because the behaviour is different in each.

All of it should end up in the test criteria for the board. Define the loads, the input range and the ripple limit for each mode, and state whether automatic light load operation is permitted. A converter whose behaviour is only documented in a conversation will produce a different conclusion in the next review, and the resulting design changes will be made against the wrong assumption.

FAQ

Does light load ripple indicate a design fault? Not necessarily. On a converter with automatic light load mode it is expected behaviour within the specified limits.

How do I keep a fixed switching frequency? Use the forced PWM option if the device provides it, and accept the standby current that comes with it.

Can output capacitance remove the low frequency ripple? It reduces the amplitude, but the pulse pattern that produces it comes from the controller and remains.

Where should the measurement be taken? At the load point, with the switch node observed simultaneously and a short ground loop on the probe.

Summary

Light load ripple on a modern converter is usually a question of which modulation mode is active, not whether the loop has failed. Look at the switch node, correlate the change with the load, read the configuration and the datasheet, and only then decide whether the behaviour exceeds the specification. Investigate in that order and the compensation network is considered last rather than first, which is where it belongs.