Low Skew Clock Buffer Fanout And Output Termination

A backplane that carries several cards, each with its own processor and its own reference clock, needs a distribution device that can drive many differential pairs with almost no difference in delay between them. The buffer is chosen on three figures: how many outputs it provides, how far apart those outputs drift from each other, and how much jitter it adds. Everything else is secondary.

This article looks at the numbers behind those three figures, at the two rail supply that such a device often needs, and at the termination that its output stage demands. The examples are drawn from a nine output device used to distribute a reference clock to nine cards.

What A Fanout Buffer Has To Guarantee

The function is simple to state: one input, many outputs, all in phase. What makes the part difficult to design is that the outputs share a supply, a bias network and a die, so any coupling between them appears as a difference in timing. The device has to isolate the channels while keeping them matched, and the datasheet expresses the result as a skew figure.

The second requirement is selectivity. A backplane may have two reference sources, one for the system and one for the line interface, and the buffer is expected to switch between them under software control. That adds a multiplexer in front of the distribution tree, and the switch has to be clean, because a glitch on a reference clock can disturb every receiver at once.

Reading The Skew Specification

Two skew figures are quoted and they must not be confused. The output skew is the difference in propagation delay between two outputs of the same device, and it is usually quoted as a typical value with a maximum. The part to part skew is the difference between two devices fed from the same source, and it is larger because it includes the variation of the internal delay with process and temperature.

For a design that distributes a clock across several cards, the part to part figure is the one that matters, because each card has its own device. A typical specification of fifteen picoseconds within a device and one hundred picoseconds between devices means that a system built from several cards has to budget the larger number. Where the receivers can tolerate a skew of a fraction of the unit interval, the budget is usually met without extra calibration.

A Two Rail Supply And What It Changes

Some devices of this class separate the core supply from the output supply, so that the internal logic runs from a higher rail and the output stage from a lower one. The arrangement improves the noise performance, because the output switching current is drawn from a rail that does not feed the sensitive input receivers, but it introduces a wiring hazard: the two rails are not interchangeable.

Applying the output rail to the core supply pin, or the reverse, destroys the device. The layout should make the two nets visually distinct, and the silkscreen or the assembly drawing should name them. Verification of the supply levels before power is applied is worth the minute it takes, because a reversed rail is not a fault that can be repaired by rework.

Open Emitter Outputs And Their Termination

An open emitter output is a transistor whose emitter is brought to the pin and whose collector is internally connected to the supply. The stage therefore sources current when it is on and relies on an external resistor to define the low level, so each output pair needs a termination to ground rather than to a supply. The value is chosen to match the characteristic impedance of the pair, typically fifty ohms per side.

The rule that catches designers out is that both halves of a pair must be terminated, even when only one is used. Leaving the unused side unterminated allows the emitter to pull it to a level that disturbs the reference of the differential stage, and the skew of the other outputs rises sharply. An unused pair, by contrast, can be left open without affecting the channels that are in use, which is a useful property when a device is specified with more outputs than the design requires.

The Enable And Select Pins

The enable and select inputs are usually compatible with the low voltage logic that controls them, so no translator is required. The useful property to look for is whether the enable is synchronous. An asynchronous enable can change the output state part way through a clock period and produce a narrow pulse that the receiver interprets as a valid edge, which can disturb a phase locked loop downstream.

A synchronous enable changes the output only when the clock is in the low state, so no runt pulse is generated. The difference is not visible on a slow measurement and is obvious on a phase noise plot or on a lock indicator. Where the clock can be switched while the system is running, the synchronous behaviour should be confirmed from the timing diagram rather than assumed from the presence of an enable pin.

Propagation Delay And Timing Budget

The propagation delay includes the internal buffer, and it varies with temperature and supply. A typical value near eight hundred and fifty picoseconds with a maximum of about one nanosecond over the full range is common. For a timing budget the maximum, plus a margin, is what should be used, because the delay is not reduced by any of the trimming that is applied elsewhere in the system.

The delay matters differently depending on the architecture. In a synchronous system where every card uses the same clock, the absolute delay affects the phase of the clock at the destination and may need to be compensated by a trace length. In a system where the clock only has to be consistent between the cards, the absolute value cancels and only the skew matters. Knowing which case applies avoids both over design and a surprise at integration. The routing techniques that keep the pairs matched are described for differential traces and for length matching, and the isolation between the pairs follows the spacing guidance of the three width rule.

Additional Considerations for This Build

Practical attention to HSTL output pays for itself here, because it decides whether the finished board behaves as the drawing intended. Where the requirement is not stated on the fabrication drawing or in the assembly notes, the shop has to assume a default, and that default is rarely the value the design was simulated with. Stating HSTL output explicitly, together with the tolerance that applies, removes the assumption and keeps the result predictable from batch to batch.

Process Control and Verification

On a design of this kind, clock buffer is the item that decides how the rest of the board is arranged. Reviewing the design before the data is released is cheaper than correcting it after the panel is in the tank, because every step downstream inherits the decision made at the front end. Documenting the assumption is part of the design work, and a short note on the drawing prevents a question that would otherwise arrive a day later and cost a day of schedule.

FAQ

Can an unused output pair be left unterminated? Yes, an unused pair can be left open, because it does not affect the channels in use. An unused half of a pair that is in use must still be terminated.

Why is the part to part skew larger than the output to output skew? It includes the variation of the internal delay with process, supply and temperature between two separate devices, while the output skew only reflects the matching within one die.

Does a synchronous enable remove the need for a clock switch? No. It removes the runt pulse that an asynchronous enable can produce, but the multiplexing between two sources still has to be arranged so that neither output is driven into the other during the changeover.