LVPECL Differential Oscillator Design Notes
A differential oscillator drives a clock as a pair of complementary signals rather than as a single ended logic level. The receiver looks at the difference, so any noise that couples equally into both conductors cancels instead of appearing as timing error. That property is what makes the differential output the standard choice above a few hundred megahertz and in any link where the clock has to travel across a board.
The electrical rules that go with the output family are specific, and a network designed for one family will not work for another. This article covers the LVPECL case: how the output is terminated, how the phase jitter figure should be read, and what the layout has to preserve.
What The Differential Output Provides
The two outputs swing in opposite directions about a common level, and the receiver amplifies the difference. Common mode noise that arrives on both conductors is rejected, which improves the effective signal to noise ratio without raising the swing. The swing itself is smaller than a single ended complementary metal oxide semiconductor clock, so the edge rate is faster and the current drawn from the supply is more nearly constant.
The trade is a fixed common mode level that is not compatible with every receiver. An LVPECL output sits at a level that suits an LVPECL or a CML input, and driving a device that expects a different common mode requires either an interface or a coupling network. Checking the common mode range of the receiver against the output level of the oscillator is the first step of any differential clock design.
Phase Jitter And Link Margin
The phase jitter figure describes the random variation of the edge position and is usually quoted in picoseconds or femtoseconds root mean square over an integration band. A value well below a picosecond is typical of a good differential oscillator, and it is what allows a high speed serialiser to sample with a small eye opening.
The integration band matters as much as the value. Jitter quoted over a wide band includes low frequency wander that a receiver with a clean phase locked loop will track out, so the figure that applies to the link is the one integrated over the loop bandwidth. Two oscillators with the same headline number can behave differently in a link for that reason, and the measurement conditions should be recorded with the figure.
The Termination Network
An LVPECL output is an emitter follower, and the stage is designed to drive a load that is returned to a level two volts below the supply rather than to ground. That is why the classic termination uses a resistor to the supply rail and a resistor to ground, or a single resistor to a bias supply at the required level. Terminating to the wrong level shifts the operating point and either clips the waveform or increases the jitter.
The network also sets the drive current. A pair terminated with fifty ohms to the correct bias draws a defined current, and a network with the wrong values draws more or less, which changes the edge rate and the power dissipation. Where a receiver has an internal termination, the external network is often replaced by a coupling capacitor and the internal bias, but the coupling capacitor must be large enough to pass the lowest frequency in the data pattern without droop.
Supply And Decoupling
A differential oscillator draws its current in pulses at the output transitions, and the supply has to present a low impedance at the harmonics of the clock. A ceramic capacitor of about 0.1 microfarad placed within a millimetre or two of the supply pin, with its ground via directly beside the pin, handles the high frequency component. A larger capacitor nearby supplies the slower transients.
Where the oscillator shares a rail with other devices, the connection should be a short branch from the plane rather than a daisy chain, so that the switching current of the oscillator does not flow through the supply path of a sensitive analogue device. The same reasoning applies to the ground return, which should reach the plane by the shortest route rather than through a shared trace.
Layout Of The Output Pair
The pair should be routed as a controlled differential line with a constant spacing, an impedance matched to the termination, and a length difference between the two conductors kept to a few mils. A length difference converts part of the differential signal into a common mode component, which then radiates or couples into adjacent traces. Above a gigahertz, a difference of a few tens of mils is enough to disturb the eye.
The pair should cross an unbroken reference plane and should not cross a plane split, because the return current has to follow the signal and a split forces it to detour, which adds inductance and an impedance discontinuity. The differential pair should be kept away from other nets by several times the trace width, and the pads of the oscillator should be connected to the plane with vias placed directly beside them. The relevant routing rules are the ones described for length matching, and the pad geometry should follow the recommended land pattern for pad design rather than an approximation, since the footprint of a small oscillator is drawn around its internal lead frame. The placement rules described for component placement also apply to the orientation of the part.
Aging And Accuracy Over Life
Three contributions add up to the frequency error seen over the life of the product: the initial tolerance at the reference temperature, the deviation across the operating range, and the ageing. Ageing is usually quoted as a figure per year for the first year and a smaller figure thereafter, and it accumulates. For a link that has to hold its rate for a decade, the ageing term is not negligible.
The duty cycle specification also matters, because a receiver that samples on both edges depends on a fifty percent duty cycle to keep the two sampling points equally spaced. A specification of forty five to fifty five percent is common and is adequate for most links, while a tighter figure is required where the clock is used directly as a data strobe. Both figures should be confirmed from the datasheet rather than assumed from the frequency accuracy.
Process Control and Verification
On a design of this kind, duty cycle is the item that decides how the rest of the board is arranged. A short note on the drawing about handling, storage or packaging is often worth more than an extra decimal place on a tolerance. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance.
FAQ
Can an LVPECL output be terminated to ground? Not directly. The stage expects a load returned to a level about two volts below the supply. A resistor to ground shifts the operating point and degrades the waveform.
Is a lower phase jitter figure always better? It is better for the link, but the figure has to be compared over the same integration band. A number quoted over a wider band includes wander that the receiver will track out.
Why does a length mismatch within the pair matter more than between pairs? A mismatch within the pair converts the differential signal into common mode, which the receiver cannot reject in the same way. A mismatch between pairs shifts the arrival time but keeps each pair balanced.
