Multilayer PCB Impedance Routing: Differential Pair Design

A differential pair carries one signal on two traces, and the receiver reads only the difference between them. That arrangement works because the two traces travel together through the same stackup, the same reference planes, and the same process window. When the geometry drifts, the pair stops behaving as one transmission line and starts behaving as two. Impedance routing on a multilayer board is therefore a design task and a fabrication task at the same time. Neither side can hold the target alone.

This article walks through the decisions that shape differential impedance on multilayer boards. It covers stackup definition, trace geometry, spacing, length matching, via transitions, and reference plane integrity. Each section explains what the designer controls, what the fabricator controls, and where the two must agree before tooling starts. Buyers and engineers can use the same structure when they review a supplier’s process. The goal is a pair that meets its target impedance across the whole route, not just on the drawing.

Why Differential Pairs Need Control

High-speed interfaces such as USB, PCIe, Ethernet, and HDMI send data as differential signals. The receiver subtracts one trace from the other, so noise coupled equally into both traces cancels out. That cancellation only works while the two traces stay electrically similar. If one trace has a different impedance, a different length, or a different return path, the cancellation weakens. Signal integrity then degrades in ways that are hard to trace back to a single layout mistake.

Impedance matching also limits reflection at the driver and receiver. A pair that holds its target impedance delivers more of the signal energy and radiates less. That matters for electromagnetic interference, because a well-coupled pair confines its fields tightly. Poor coupling spreads the fields and turns the pair into an unintended antenna. The design choices below all serve the same purpose: keep the pair coupled, symmetric, and referenced to a solid plane from end to end.

Stackup Choices Set the Target

Impedance cannot be controlled by specifying a trace width alone. The value depends on trace width, dielectric thickness, dielectric constant, and copper thickness together. A stackup that fixes dielectric thickness gives the designer a stable base for calculation. A stackup built from available core and prepreg combinations gives the fabricator room to hit the target. The two views must be reconciled before routing begins, because moving a signal layer later invalidates every impedance calculation on that layer.

For a controlled-impedance design, engineers should define the target differential impedance, the reference plane for each signal layer, the dielectric thickness under each trace, and the copper weight. They should also state the tolerance window and the test coupon pattern. The fabricator then confirms which material combinations can meet those numbers in production. If the answer is no, the stackup changes, not the target. Resolving this early avoids a redesign after the first article.

Trace Geometry and Spacing

Differential impedance depends on the width of each trace and the gap between them. Widening the traces lowers the impedance, and increasing the gap raises it. Designers usually start from a calculation tool and then ask the fabricator to confirm the result with the actual material data. A common starting point is a gap near twice the trace width, but that is a habit rather than a rule. The final gap should come from the target impedance and the confirmed stackup.

Spacing must also stay constant along the route. Every change in gap changes the coupling, which changes the local impedance. Bends, neck-downs at component pads, and escapes from fine-pitch packages all create such changes. Where a neck-down is unavoidable, keep it short and keep both traces symmetric through it. A pair that narrows on one side only will convert part of the differential signal into common-mode noise. That conversion is difficult to fix later and expensive to diagnose in the lab.

Routing Symmetry and Corners

The two traces should run parallel and mirror each other as closely as the layout allows. Sharp ninety-degree corners create a local change in width and coupling, so gentle bends or curved routing are preferred. The pair should also keep a consistent distance from other traces and from plane edges. Coupling to a nearby aggressor adds noise that the differential receiver cannot cancel. Where the pair must pass close to other high-speed nets, increase the gap or add a ground guard trace with stitching vias.

Component placement drives much of this. Placing related components close together shortens the pair and reduces the number of obstacles it must cross. Series components such as AC coupling capacitors or termination resistors should sit symmetrically in both traces. Align them vertically or horizontally so both sides see the same pad geometry and the same discontinuity. A capacitor placed on one trace only, or offset on one side, breaks the symmetry that the pair depends on.

Length Matching and Skew

Both traces in a pair must arrive at the receiver at nearly the same time. A length mismatch creates timing skew and reduces common-mode rejection. The allowable mismatch depends on the interface, the data rate, the dielectric, and the system timing budget. A fixed number such as five mil is a working example, not a universal requirement. Designers should take the limit from the interface specification and confirm it with the system timing analysis before release.

In real layouts, perfect matching is often impossible. Connector pinouts, BGA breakouts, and via placement can force one trace to run longer. When that happens, add controlled compensation near the point where the mismatch occurs rather than at the end of the route. A tuning pattern placed close to the source of the skew corrects the timing where it matters. Keep the tuning amplitude small and the spacing consistent, so the compensation does not create a new impedance discontinuity of its own.

Vias and Reference Planes

Every layer transition introduces parasitic inductance and capacitance, and both disturb the local impedance. A pair should change layers with both traces transitioning together and with ground vias placed close by. The return current needs a short path between reference planes, and ground stitching vias provide it. A pair that changes layers without a nearby return path forces current to spread across the plane, which raises inductance and radiates energy. This is one of the most common causes of unexpected emissions.

Reference plane integrity matters just as much along the route. A pair crossing a split or slot in its reference plane loses its return path and behaves unpredictably. Route the pair over solid copper, and keep the plane continuous under the whole length. If the pair must cross a plane boundary, provide stitching or a bridge capacitor so the return current can follow. Buyers should ask how the fabricator checks plane continuity and how the design review catches split-plane crossings before tooling.

Verification Before Release

Before releasing a high-speed multilayer design, engineers should verify the stackup against the fabrication drawing, the impedance targets against the calculation, and the routing against the length and spacing rules. They should confirm that test coupons exist for each controlled layer and that the acceptance window is written down. A design review that covers these points costs little and catches problems while they are still in the file. A PCB design and layout review at this stage is cheaper than a respin.

Fabrication verification continues the same logic. The fabricator measures impedance on coupons and reports the result against the target. First-article approval should include those measurements, not just a visual check. Assembly and test then confirm that the finished board behaves as designed. A PCBA testing plan that includes functional checks on the high-speed interfaces closes the loop between design intent and delivered hardware. Documentation ties these steps together and keeps every team working from the same numbers.

Working With the Fabricator

Impedance control is a shared responsibility, and the handoff between designer and fabricator decides the outcome. The designer sets the target and the geometry. The fabricator selects materials, controls etch, and measures the result. When both sides work from the same stackup document, the first article usually lands inside the window. When the stackup is left open, the fabricator makes assumptions that may not match the design. Buyers should ask for the stackup, the impedance report, and the coupon data as routine deliverables.

For projects that combine fabrication with assembly, the same discipline carries through. A turnkey PCB assembly supplier that also controls fabrication can align the stackup, the routing rules, and the test plan under one engineering review. That reduces the chance of a mismatch between the bare board and the assembled unit. Where the design is still moving, an SMT PCB assembly partner that reviews files early can flag placement issues that affect pair symmetry.

And a PCB assembly quote that includes impedance verification is easier to compare than one that leaves it out.

The practical takeaway is to settle the stackup and the impedance targets before routing starts, then verify them with measured coupon data at first article. Keep the pair symmetric, keep the reference plane solid, and keep the length compensation close to the skew. Ask the fabricator for the material data used in the final calculation, and write the acceptance window into the fabrication drawing. Those steps cost little at the start of a project. They save a respin, a field return, and a difficult conversation later in the build.