8-Layer PCB Prototyping: Stackup and Lead Time
When Four and Six Layers Stop Working
Most designs begin on four layers and move up when the layout stops closing. The move to eight is usually triggered by a specific requirement rather than by component count: a differential pair that needs a continuous reference, an analogue section that has to be isolated from a digital one, or a ball grid array whose escape routing will not fit in the space available.
Once a design needs controlled impedance on several interfaces at once, a complete return path under every high-speed signal, and separate analog and digital regions, eight layers becomes the point at which those requirements can be satisfied without compromise. Field programmable gate arrays, application processors, high-speed converters, and radio modules all tend to push a design across that line.
A Typical Stackup
The common arrangement is signal, ground, signal, power, ground, signal, power, signal. The logic behind it is that every signal layer is adjacent to a plane: the outer layers reference the ground and power planes directly below them, and the inner signal layers are sandwiched between planes on both sides.
That symmetry is deliberate. It keeps the board balanced through lamination, which controls bow and twist, and it gives the inner layers stripline geometry with predictable impedance. The two power planes can be assigned to different rails, or one can be split between rails where the current is modest and the splits are kept clear of the high-speed routing.
Thin dielectric between the power and ground planes is chosen for two reasons: it improves the interplane capacitance that supplies high-frequency transient current, and it lets the outer signal layers reach a useful impedance with a trace width the fabricator can actually etch.
What Makes a Fast Prototype Difficult
Every additional pair of layers adds a lamination cycle, and every lamination cycle adds a registration step where the inner layers must align to a tolerance measured in tens of microns. A stack with blind or buried vias adds drilling and plating operations that occur between laminations, and each of those is an opportunity for the panel to be scrapped late in the process, when most of the value has already been added.
Impedance verification is the other difficulty. The design assumes a dielectric height that the press must deliver, and the etch must produce a trace width that matches the model. On a quick-turn schedule there is little time to iterate, so the fabricator either holds the process tightly enough the first time or the boards arrive out of specification. This is why quick-turn multilayer prototyping is a capability question rather than a scheduling one: the same cycle time is available to every factory, but only some of them have the process control to use it well.
Lead Time
A conventional eight-layer order in production quantities typically runs ten to twelve days. Quick-turn services compress that to somewhere between three and five working days, and the fastest turnarounds reach seventy-two to one hundred and twenty hours for simple stacks.
Several things have to line up for that to happen: the laminate has to be in stock rather than ordered, the hole structure has to be within the routine capability, and the surface finish and electrical test must be standard rather than special. A design that needs a rare material, an unusual finish, or an impedance requirement the shop has to develop is not a quick-turn job no matter what the quotation says.
Materials for an Eight-Layer Prototype
Mid-grade FR-4 with a glass transition temperature of 150 to 170 degrees covers most prototypes. Higher Tg grades are chosen where the assembly involves multiple reflow cycles or where the operating temperature is elevated, and low-loss laminates appear when the design carries radio-frequency signals or very fast serial links.
Mixed constructions are common: a low-loss material on the high-speed layers and standard FR-4 elsewhere, laminated together. The approach saves cost but requires the fabricator to manage different materials in one press cycle, so it is worth confirming that the shop has done it before rather than discovering the difficulty on the first panel.
Getting the Design Ready
A design review before release saves more time than any expedited shipping option. The stackup should be drawn explicitly with dielectric thicknesses and copper weights, and the impedance targets should be stated with their tolerance. Via structures should be described as through, blind, or buried, with the aspect ratios the fabricator is being asked to hold.
Panelisation deserves attention because it affects both cost and schedule: a board that tiles efficiently uses the panel and reduces the price, while one that leaves large unused areas pays for them anyway. The surface finish should be chosen for the assembly that follows the prototype, since a finish selected for convenience may not survive the storage and reflow of the evaluation build.
Testing the Prototype
Electrical test confirms continuity and isolation across every net, and impedance coupons measured with time-domain reflectometry confirm that the stack behaved as designed. Automated optical inspection catches pattern defects, and X-ray is needed where the prototype already carries a ball grid array. Microsection on a sample shows the dielectric heights and the plating thickness that the electrical measurements only inferred.
For a prototype the value of that data is not the pass or fail result but the feedback it provides before the design is frozen. A stackup that measures off its target impedance on the coupon will do the same in production, and correcting it before the layout is committed costs nothing compared with discovering it after the design has been released.
What It Costs
Prototype pricing is dominated by setup. The tooling, the inner layer films, the lamination cycles, and the engineering review are fixed costs spread across a small number of boards, which is why the first five pieces cost far more per unit than the first five thousand.
Expediting adds a premium because the factory re-sequences its work, and non-standard materials or structures add more. The sensible approach is to keep the design inside the shop’s standard capability, order the quantity the evaluation actually needs, and reserve the expedite fee for the schedule that genuinely requires it. A supplier that can quote PCB manufacturing for the prototype and then carry the design into PCB assembly without a handover is usually the cheaper option once the engineering time is counted.
FAQ
How fast can an eight-layer prototype be made? Three to five working days is typical for quick-turn service, with seventy-two to one hundred and twenty hours achievable on simple stacks when materials are in stock.
Why not start with six layers? Six is usually adequate until the design needs multiple impedance-controlled interfaces, several BGA escapes, or genuinely separate analog and digital regions with their own references.
What does the stackup look like? Signal, ground, signal, power, ground, signal, power, signal is the common eight-layer arrangement, with every signal layer adjacent to a plane.
Is a mixed-material stackup worth it? Sometimes. It saves cost where only one or two layers need low loss, but it requires a fabricator experienced in pressing different materials together.
How is impedance confirmed on a prototype? With test coupons measured by time-domain reflectometry, and with microsection on a sample to confirm the dielectric heights the impedance depends on.
Conclusion
Eight-layer prototyping is the point at which a design’s electrical requirements and the fabricator’s process control meet. The stackup provides the references and the impedance control the design needs; the schedule depends on whether the shop can hold registration and dielectric height on the first pass. Getting the stackup, the hole structure, and the panelisation right before release is what makes a fast turnaround real rather than optimistic. For related topics, see our notes on PCB design and layout and PCB capabilities.
