Why Impedance Changes Along a High Speed Trace

A Trace Is Only a Transmission Line While It Behaves Like One

Once signal edges become fast enough that the rise time is short compared with the trace length, the interconnect stops behaving like a wire and starts behaving like a transmission line. At that point, what matters is not whether the net is connected but whether its characteristic impedance is constant from driver to receiver. Every place where that impedance changes, part of the signal energy reflects back toward the source, and the consequences accumulate: ringing, overshoot, added jitter and a closing eye diagram.

This is the practical problem engineers face on PCIe lanes, DDR interfaces, 100 gigabit Ethernet channels and any other interface running at gigahertz rates. This guide covers what determines impedance, where discontinuities come from in design and in manufacturing, how they are measured and analysed, and what can be done about them.

What Determines Trace Impedance

Characteristic impedance is set by the interaction of resistance, inductance and capacitance along the transmission line, and in practice those reduce to a small set of physical parameters. Trace width. Copper thickness. The dielectric properties of the laminate between the trace and its reference. The distance between the trace and the reference plane. And the presence and continuity of the reference plane itself.

Two impedance families matter most. Single ended impedance, measured against a reference plane, is typically designed at 50 or 75 ohms and appears in radio frequency circuits and many high speed digital interfaces. Differential impedance describes a pair of coupled traces and is typically designed at 90, 100 or 120 ohms, appearing in USB, HDMI, PCIe, Ethernet and DDR memory interfaces. For every one of those, consistency along the entire path is the design objective. A trace that is 50 ohms for most of its length and 42 ohms for a short section is worse than a trace that is uniformly 46 ohms.

What a Discontinuity Is

An impedance discontinuity is any point where the impedance changes abruptly. The common locations are a sudden change in trace width, a signal layer transition through a via, a connector interface, and a change in the dielectric material along the path.

When a high speed signal crosses such a point, part of its energy reflects back toward the source. The visible symptoms are reflection, ringing, overshoot, increased timing jitter and a rising bit error rate. On systems like PCIe, DDR5 or 100 gigabit networking, even a modest impedance excursion in the wrong place is enough to push a channel outside its compliance margin.

Causes in Manufacturing

Trace geometry variation. Etching tolerance changes trace width and copper thickness and leaves the line edges slightly irregular. A variation of a few microns is enough to move characteristic impedance measurably, which is why etch control is a controlled impedance parameter rather than a general workmanship item.

Material variation. Dielectric constant directly determines propagation velocity and impedance. Variation arises between laminate batches, from differences in resin content and from lamination process differences. This is why material specification for a controlled impedance board includes dielectric constant tolerance, not just the nominal value.

Stackup design. Uneven dielectric thickness, a discontinuous reference plane, or an error in layer spacing all shift impedance away from the target. On a high speed design the stackup must be agreed with the fabricator at design stage, because it is a manufacturing constraint as much as an electrical one. The design side of this is covered under PCB design and layout.

Via structures. Vias are the most common source of discontinuity in practice. A through via leaves an unused barrel section, or stub, below the layer where the signal enters; that stub behaves as an open circuited transmission line, producing a resonance that degrades the channel. Oversized via pads and poorly designed anti-pads add capacitance, and reference plane voids around the via break the return path.

Process tolerance. Etch precision, plated copper thickness, solder mask thickness and lamination pressure all influence the finished impedance. A fabricator holding controlled impedance capability controls these parameters deliberately and verifies the result, rather than treating them as incidental.

How the Effects Show Up

Five symptoms appear in sequence as discontinuity severity increases. Signal reflection, where energy returns toward the source and the waveform distorts. Crosstalk, where the reflected energy couples into adjacent traces. Timing error, expressed as increased jitter, delay variation and clock skew. Eye diagram degradation, where the opening narrows and the margin to the mask shrinks. And higher bit error rate in the finished link. The eye diagram consequence is worth following in detail, since it is the measurement most programmes actually specify; our notes on eye diagram analysis explain how the effects of impedance variation appear there.

Analysis Methods

Time domain reflectometry. The standard measurement. A fast pulse is launched into the trace and the reflected energy is recorded, so impedance can be plotted against distance and the location of every discontinuity identified. It is the technique fabricators use on impedance coupons and the technique engineers use to debug a failing channel. The practical application is described under TDR impedance testing.

Signal integrity simulation. Pre-layout and post-layout simulation identifies impedance problems before fabrication. The modelling has to include the via structures and the stackup as they will actually be built, because simulating an idealised stackup gives an optimistic result.

Vector network analysis. Used mainly for radio frequency boards, measuring return loss, insertion loss and frequency response across the band of interest. Where a channel operates over a wide band, VNA data describes its behaviour more completely than a single TDR reading.

Impedance coupons. Fabricators build test coupons on the production panel and verify the achieved impedance with TDR, which is how a controlled impedance claim is substantiated on a real production lot rather than on a simulation.

Manufacturing Factors That Govern Impedance

Five process variables determine the finished result: laminate dielectric constant, copper foil thickness, etching precision, lamination process and drilling accuracy. A fabricator with a mature controlled impedance capability models the stackup, controls each of these parameters, and verifies the outcome with coupon measurement. Impedance tolerances typically specified are plus or minus ten percent for general boards, plus or minus five percent for high speed designs and plus or minus three percent for high frequency radio frequency work. Those bands are progressively harder to hold and progressively more expensive to guarantee.

Engineering Remedies

Design the stackup precisely. Fix the impedance structure at design stage rather than adjusting it later, and specify it in terms the fabricator can build to.

Control the routing rules. Keep trace width consistent, keep pair spacing consistent, and maintain a continuous reference plane under the entire length of every high speed net. Plane splits and voids under a trace are among the most damaging and most easily avoided discontinuities.

Optimise via structures. Minimise the number of layer transitions. Where a through via is unavoidable on a high speed net, use back drilling to remove the stub; where routing allows, use blind or buried vias to eliminate the stub by construction. Keep via pads and anti-pads to the minimum the design rules allow, and provide adequate ground return vias near the signal via.

Simulate before release. Complete signal integrity simulation with realistic models before committing to fabrication. A simulation that assumes perfect geometry will not predict a channel that passes in the lab and fails in production.

Work with the fabricator early. The single most effective practice is engaging the fabricator on the stackup before the layout is frozen, because most impedance problems originate in decisions made at that stage. An impedance controlled build is described under controlled impedance manufacturing.

Common Transmission Structures

Three structures account for almost all high speed routing. Microstrip, an outer layer trace referenced to an inner ground plane. Stripline, a trace buried between two reference planes, which provides better isolation and is preferred for sensitive nets. And differential pairs, two coupled traces routed together where the coupled impedance is the design target. Each has a different sensitivity to manufacturing variation: microstrip impedance depends on trace width more strongly, while stripline depends more on dielectric thickness and is therefore more sensitive to lamination control.

Controlled Impedance Process

A controlled impedance programme runs through five stages: stackup design, impedance calculation, fabrication, impedance measurement and final quality verification. Established fabricators use automated impedance modelling and control systems to keep results stable across a production run, and provide the coupon measurements as evidence. That evidence is what makes the tolerance claim meaningful.

Cost

Controlled impedance boards carry a premium over general purpose boards, driven by layer count, laminate type, board size, via structure and order quantity. Indicative pricing for 2026 in US dollars, per panel, is roughly 80 to 200 for a four layer high speed prototype, 150 to 400 for a six layer high speed board, 400 to 900 for an eight to twelve layer high speed board, and 800 to 2,000 for a high frequency radio frequency board using materials such as Rogers. Our notes on custom PCB pricing explain how these variables combine.

Selecting a Manufacturer

Four capabilities matter: demonstrated impedance control capability rather than a stated willingness to try, in-house test equipment so that coupons are measured rather than assumed, engineering support that can discuss stackup and simulation with the design team, and a stable material supply so that the laminate actually used matches the one the impedance was calculated against. Material substitution without re-calculation is one of the most common causes of a controlled impedance board arriving out of tolerance.

Questions Engineers Ask

Why does impedance discontinuity occur? Trace width variation, dielectric variation between batches, unsuitable stackup, via structures and manufacturing process tolerances, in roughly that order of frequency.

How is impedance controlled in production? By controlling trace width, dielectric thickness, copper thickness and laminate parameters, and then verifying with TDR measurement on coupons.

What impedance tolerance is normal? Plus or minus ten percent for general boards, five percent for high speed designs and three percent for high frequency radio frequency work.

Do vias cause discontinuities? Yes. The stub left by a through via is the most significant contributor, along with pad and anti-pad geometry and reference plane treatment.

What reduces discontinuity most effectively? A stackup designed with the fabricator, uniform routing rules, fewer layer transitions with back drilling or blind vias where needed, realistic simulation before release, and a manufacturer with genuine impedance control experience.

Conclusion

Impedance discontinuity is not a single defect but the cumulative result of many small deviations, most of which originate in design decisions and are realised in manufacturing variation. The remedy follows the same pattern: define the stackup precisely and agree it with the fabricator, keep geometry and reference planes consistent along the whole path, control via structures deliberately, simulate with realistic models, and verify the finished board by measurement rather than assumption. As data rates continue to rise, the margin available for these deviations will keep shrinking, and the discipline will keep mattering more.