PCB Miniaturisation: Principles, Limits and Cost

What Miniaturisation Means in Practice

Miniaturising a board means fitting the same circuit into less area, less thickness or less weight, without giving up performance. It is not one technique but a set of them applied together, and the useful ones depend on what is actually limiting the size of the product.

Three different constraints hide behind the same word. Sometimes the board is too large and the answer is more routing layers and finer geometry. Sometimes it is too thick and the answer is a thinner laminate and a thinner solder mask. Sometimes it is too heavy, which is a different problem again and is usually solved with a flexible circuit rather than a smaller rigid one. Knowing which constraint applies is the first step, because the techniques that shrink the area are not the ones that reduce the thickness.

Thinner Materials

The quickest reduction in thickness comes from the laminate and the copper. A standard board is 1.6 millimetres thick with one ounce copper, but 0.8, 0.6 and even 0.4 millimetre laminates are routinely available, and half ounce copper is used where the current permits. The thickness of the finished assembly is then dominated by the components and the connector rather than by the board.

The penalties are mechanical. Stiffness falls with the cube of the thickness, so a thin board flexes under the weight of its own components and needs support in the housing or during assembly. Thin laminates are also harder to process: they bow during lamination and can wrap around rollers in the conveyor. A thin board is usually specified with a handling panel or a stiffener frame to carry it through the assembly line.

Fine lines and thin laminates also make the dielectric thinner, which lowers the breakdown voltage and increases the capacitance to the reference plane. On a low voltage digital board that is harmless; on an isolated or high voltage section it is a constraint.

Stacking and Layer Count

Once the single layer routing is exhausted, adding layers is the way to reduce area. A four layer board with two routing layers and two planes typically occupies half to two thirds of the area of the same circuit on two layers. Six layers with a ground plane beside each routing layer continues the trend, and the return path control improves at the same time.

Beyond the ordinary stack, high density interconnect construction uses laser drilled microvias with a diameter well below the mechanical drill limit, sequentially laminated so that vias can connect only the layers they need. That structure is what allows a phone mainboard to fit in the space of a business card, and it comes with a substantial cost and a much tighter process window.

Two rules keep the stack sane. Do not add layers for the sake of it, because a four layer board with a good layout usually outperforms a six layer board with a poor one. And keep the stack symmetrical, because a thin asymmetrical board warps during lamination and reflow.

Fine Pitch Components and Microvias

Miniaturisation is limited by the components as much as by the board. A fine pitch package forces a smaller track width and spacing, a thinner mask dam between pads, and often a via placed inside the pad. All three are achievable, and all three raise the fabrication requirement and reduce the process margin.

The via in pad construction is the one that most often causes trouble. A via inside a pad must be filled and plated over, or the solder paste wicks down the hole and leaves a void in the joint. That means an additional filling step, a planarisation step and a plating step, and it is the point at which a board moves from ordinary fine line work into high density interconnect territory. Our notes on PCB manufacturing describe how the filling and plating are controlled.

Thermal Limits

A smaller board with the same power dissipation has a higher power density, and the heat has less copper and less area to escape through. That is the limit that most often stops a miniaturisation programme.

The answers are the ordinary ones applied more aggressively. Use more copper on the ground layer as a heat spreader, add thermal vias under the hot components, move the heat into the housing through a thermal pad or a metal core section, and accept a higher component temperature if the reliability analysis supports it. Where the board cannot carry the heat, the solution is often to move the hot circuit off the small board onto a separate one that has the area to dissipate, which is a system decision rather than a layout one.

What Miniaturisation Costs

The board cost rises steeply at the small end. As an indication, a small batch of miniaturised boards runs roughly 50 to 150 US dollars per board for small quantities, depending on the complexity and the layer count, against a few dollars for a conventional two layer board of similar circuit. The premium comes from the fine lines, the microvias, the thin laminate, the sequential lamination and the yield loss.

Assembly cost rises too, because the placement accuracy has to be higher, the stencil is thinner and the inspection is more demanding. And the cost of a design error rises with all of the above, which is why a miniaturisation programme usually starts with a prototype that is deliberately larger than the target, to prove the circuit before the geometry is compressed.

Risks and Failure Modes

Microcracks in the laminate. Handling a very thin board, and the mechanical stress of the assembly and the housing, can crack the resin around the vias. The fix is mechanical support rather than a process change.

Voids under fine pitch joints. A via in pad that is incompletely filled, or a paste volume that is slightly high, produces a void that passes inspection and fails in the field.

Registration error. With finer lines the same absolute registration error consumes a larger proportion of the spacing, so the process capability of the fabricator matters more than the nominal dimension. Our notes on quality management describe the process control that keeps it in check.

Thermal runaway in a confined space. A dense board inside a sealed housing has no convection path. The thermal design has to assume the worst case ambient, and the test has to be run in the enclosure rather than on the bench.

Where It Is Used

• Consumer electronics. Smartphones, tablets, smart watches and earbuds, where the board area is fixed by the industrial design.
• Wearables. Health trackers and hearables, where weight matters as much as area and a flexible or rigid flex construction is common.
• Medical devices. Portable diagnostics, implantable electronics and catheter based instruments.
• Automotive and aerospace. Sensor modules, control units and avionics, where the reduction in weight has a direct effect on the vehicle.
• Industrial and IoT sensors. Compact sensor nodes that have to fit inside an existing machine or an existing enclosure.

Design Practice

Decide what is actually constrained. Area, thickness and weight have different solutions, and the ones that matter should be named at the start.

Stay inside the fabricator capability. A design at the very edge of the capability has no margin for the inevitable process variation. Ask for the recommended values, not the absolute minimums.

Design the thermal path with the layout. On a dense board the copper that carries the ground also carries the heat, and both functions have to be planned together; our notes on PCB design and layout cover the techniques.

Keep the test access. It is tempting to remove the test points when space is short, and it is a mistake. A dense board that cannot be probed is very expensive to debug, so bring the critical nets to small pads or vias. Our notes on PCB assembly describe the assembly and inspection consequences of the fine geometry.

FAQ

How small can a PCB be? With microvias and high density interconnect construction a fully functional board can be a few square centimetres, and the practical limit is usually the components and the connectors rather than the board.

Does miniaturisation reduce performance? Not if it is done well. Shorter signal paths reduce parasitic inductance and capacitance, so the electrical performance often improves. The risk is thermal and mechanical, not electrical.

What does a miniaturised board cost? Small quantities typically run 50 to 150 US dollars per board, depending on the layer count and complexity, against a few dollars for a conventional board.

What is the single biggest limit? Heat. A smaller board has less area to dissipate the same power, and the thermal design decides how far the geometry can be compressed.

Conclusion

Miniaturisation is a set of trade-offs rather than a single technology. Thin laminates reduce thickness at the cost of stiffness, extra layers and microvias reduce area at the cost of yield and money, and fine pitch components demand a process window that leaves no room for error. Decide which dimension is actually constrained, plan the thermal path with the layout, keep the test access, and prototype above the target density before compressing the design.