Design for Testability: DFT Rules for PCB Assembly
What Design for Testability Means
Design for testability is the practice of making a board easy to verify, so that a fault introduced during manufacture is found before the product leaves the factory rather than by the customer. It is a design activity, not a test activity: once the board is fabricated, the test access that was not provided cannot be added.
The stake is larger than it first appears. Test coverage decides the escape rate, the escape rate decides the field failure rate and the support cost, and the test method decides how much time each board spends on the line. A board designed for test is cheaper to verify and more reliable in service than an identical circuit that was not.
The Test Stages
Automated optical inspection. Cameras check the paste deposition and the solder joints for the defects that are visible from above, such as a missing component, a tombstone, a bridge or a shifted part. It catches the majority of assembly defects quickly and needs no test points, but it cannot see under a package.
X-ray inspection. Used for the joints that cannot be seen, particularly the ball grid array and the bottom terminated packages. It verifies the solder volume and the presence of voids and bridges, and it is the only practical check for a hidden joint.
In circuit test and flying probe. These methods contact the board and measure component values, continuity and isolation. In circuit test uses a dedicated fixture with a bed of nails; flying probe uses moving probes and needs no fixture, which suits prototypes and low volumes. Both need accessible pads on the board.
Boundary scan. Devices that support it can drive and read their own pins, which allows the connections between them to be verified without physical access. It is the standard answer for a board where the density leaves no room for test points.
Functional test. The board is powered and exercised as it will be in the product. It is the most realistic test and the most expensive to develop, and it is normally combined with one of the access methods above.
DFT Rules for the Layout
Provide test points on the accessible nodes. A test point is a defined pad that a probe can contact, its own copper area rather than a component pad, so that the probe does not damage a solder joint. Where a node cannot have a dedicated pad, an existing pad or a via may be used if the probe geometry allows it.
Keep the test side clear. Test points are usually placed on the solder side in a regular grid, with a defined keep-out around each one so that the probe and its fixture can reach it. Components, tall parts and connectors near a test point will block the probe.
Size and spacing. The pad diameter, the spacing between pads and the distance from a test point to the board edge are all fixed by the tester and the fixture. They should be taken from the assembly house rather than assumed, because a change of tester changes the rules.
Protect the critical nets. Power rails, ground, reset, clocks, the programming and debug interfaces and the key analogue measurement nodes should always be accessible, because those are the nodes that diagnose the majority of faults. Full node access is the ideal; a well chosen subset of perhaps eighty percent of the nodes catches most defects at a fraction of the fixture cost.
Prefer one test side. A single sided test fixture is much cheaper than a double sided one, so the design should cluster the test points on one side wherever the circuit permits.
Add the tooling features. Fiducials for the placement machines and the optical inspection, tooling holes for the fixture and the panel rails for handling are all part of the design, and they have to be placed so that they do not conflict with the keep-outs.
Design for boundary scan. Where the design uses devices with boundary scan, the chain should be routed as a controlled impedance path from device to device, with the pull resistors on the correct pins, the correct power sequencing for the chain and the test access brought to a connector. A chain that is broken by an unpowered device or a missing pull-up does not work. The fabrication decisions that the test depends on, such as the mask treatment over the test pads and the finish on the probe surfaces, are covered in our notes on PCB manufacturing. Our notes on PCB design and layout cover the layout practices involved.
Coverage Against Cost
Test coverage is a trade. Adding test points increases the fixture cost, adds pad area and can conflict with the density of the board; reducing them lowers the fixture cost and the assembly complexity but raises the escape rate. The decision should be made from the consequence of a fault: a safety critical product justifies a high coverage scheme, while a low cost consumer accessory may be well served by optical inspection plus a functional test.
Test time is the other half of the cost, because every board spends line time in the tester. A test that covers five hundred nodes in ten seconds is cheaper per board than one that covers the same nodes in sixty, but the coverage may be identical. The order of the test, the settling time of the measurements and the number of measurement passes are design choices in the test program that the hardware should support. Our notes on PCBA testing describe how the stages are combined.
Common DFT Mistakes
The most frequent is placing a test point under a component, which makes it invisible and inaccessible once the part is mounted. The second is a test point on a node that is also a high speed signal, where the stub from the test point degrades the signal and the pad adds capacitance. The third is a test point on a node that is not stable during the test, such as a signal that is driven by a device in a reset state, which produces a measurement that cannot be interpreted.
Others include leaving no ground test points, which makes a stable measurement impossible; placing the test points only on one net class and not on the power rails; and forgetting the fiducials and tooling features, which stops the fixture and the placement machine from working at all. Each of these is cheap to fix in the layout and impossible to fix afterwards.
Documentation for Test
The assembly house needs more than artwork. The test point report, the netlist, the assembly drawing, the bill of materials with the reference designators and the component values, and the boundary scan description files are the inputs that allow a test program to be built. Where the product is programmable, the firmware and the programming procedure have to be provided as well, together with the sequence in which the device is programmed and tested, because a board that is programmed after the test cannot be verified in the test.
What Drives the Cost
Fixture cost scales with the number of test points, the number of sides and the density, and it is a fixed charge that a low volume programme feels heavily. The test program development, the functional test hardware and the programming station are further fixed costs, and the line time is the variable cost per board.
The design decisions that reduce the total are a single sided test fixture, a well chosen subset of critical nodes, a boundary scan chain to cover the inaccessible nets and a functional test that runs quickly. Spending on coverage that the product does not need is as wasteful as skipping the coverage that it does. Our notes on quality management describe how the test data is used to control the process.
FAQ
How many test points should a board have? As many as the design can accommodate on accessible nodes, with the critical nets covered first. Full access is the ideal and a well judged subset of around eighty percent of the nodes is the practical compromise.
Can a via be used as a test point? Often yes, if it is not covered by solder mask and the probe geometry allows it, but a via that is tented or filled is not accessible.
What if the board is too dense for test points? Use boundary scan for the digital nets, X-ray for the hidden joints and a functional test for the rest, and provide test points only for the power rails and the diagnostic nodes.
Why does the test point placement matter so much? Because the fixture can only reach what is exposed. A test point under a component or inside a connector keep-out is as good as absent.
Does DFT apply to a prototype? Yes, in the sense that the critical nodes should still be accessible, and flying probe can be used instead of a fixture to keep the cost down at low volume.
Conclusion
Design for testability is a layout discipline that decides how much of the manufacturing defect population is caught. Provide accessible test points for the critical nodes, keep the test side clear, define the pad geometry from the tester’s rules, use boundary scan where the density leaves no access and combine the stages so that the optical, X-ray and electrical tests each cover what the others cannot see. Done at the design stage, it is nearly free; left to the test house, it is an escape waiting to happen.
