Stacked Via: 5 Rules for HDI Reliability

A stacked via is a microvia placed directly on top of another microvia, so the connection passes through two or more HDI layers without a landing pad between them. The arrangement saves the space that an offset or staggered build would need, which is why dense BGA escapes depend on it. It also concentrates every drilled and plated feature on a single axis, and that concentration is the source of most reliability trouble in an hdi pcb.

The benefits hold only when the via fill, the plating and the layer registration are all controlled. A stacked via that is filled incompletely keeps a void in the middle of the stack, and a void under a pad becomes a blow out during reflow. Aspect ratio, meaning the depth to diameter relationship, decides how much of the wall can be plated evenly, so the whole structure has to be designed as one system.

What a Stacked Via Structure Is

A microvia is a small hole, usually between fifty and one hundred and fifty microns across, drilled through a single dielectric layer and plated to connect two adjacent copper layers. When the next layer is added, a second microvia can be placed on the same centreline, and the pair forms a stacked structure. Repeating that gives a vertical connection through the whole build up.

The alternative is a staggered build, where each microvia lands on a short pad and the next one is offset sideways. Staggering is easier to plate and easier to inspect, but it consumes routing area on every layer. Stacking recovers that area at the cost of process control, and the choice between them should be made deliberately rather than by habit.

Why Stacked Via Stacks Fail

The common failure is a crack at the interface between two vias, where the copper of one barrel meets the copper of the next. Thermal expansion pulls that joint in shear on every cycle, and any weakness there grows until the connection opens. The second common failure is separation at the target pad, where the capture pad under the via lifts from the resin.

Resin recession is the third. If the dielectric pulls back during cure, the barrel loses support and the plating becomes the only load path. Managing all three means controlling the fill material, the plating thickness and the cure profile rather than inspecting the finished hole, because the defects start in operations that happen long before the finished board exists.

Laser Drilling and Dielectric Thickness

Microvias are usually formed by laser, and the energy needed scales with the dielectric thickness that has to be removed. Thin, uniform dielectric is much easier to drill cleanly than a thick layer with uneven resin content. Where the layer is too thick, the hole tapers, the bottom diameter shrinks, and the plated connection is smaller than the drawing assumes.

Drill quality also depends on the copper foil below, which acts as a stop. A rough or inconsistent surface scatters the beam and produces an irregular target pad. Material selection therefore sets the achievable microvia size, and choosing a laminate with stable thickness and clean glass distribution makes the rest of the process far more predictable.

Via Fill Chemistry and Planarity

A stacked via is normally filled before the next layer is laminated, so the surface over the via matches the surface of the surrounding copper. Filling can be done with electroplated copper or with a conductive paste, and the two behave differently under thermal cycling. Copper fill gives the better electrical and thermal path, while paste fill is faster to apply.

Planarity is the measurement that matters. A dimple that is too deep leaves a depression that the next dielectric layer has to bridge, and that depression is where a void forms. A surface that domes above the copper creates a bump that can disrupt the next lamination. Both directions should be specified with a tolerance, not left to the supplier’s default.

Plating Thickness Inside the Via

The plating thickness on a microvia wall is not the same as the thickness on the board surface. The via wall is a small, deep feature, and the chemistry reaches it more slowly than it reaches the outer layers. For that reason the minimum thickness in the wall, measured at the mid point, is the number to specify and to verify.

Cleaning before plating matters as much as the plating current. Resin smear left by the laser has to be removed so the copper can anchor. A micro etch step that is too aggressive removes copper from the target pad, and one that is too weak leaves residue behind, so the window has to be measured on both sides.

Registration Between Layers

Every microvia in a stack has to land on the one below with enough capture to survive drift. Registration tolerance accumulates layer by layer, and a stack of three or four vias can consume the whole budget. Design should therefore start with a target pad that is larger than the drilled diameter by an amount that reflects the real registration capability of the shop.

Registration is also affected by material movement during lamination. Where the design is tight, the panel should be checked during CAM review against the actual capability rather than the nominal drawing, because a stack that is impossible to register will be built at a yield loss that accumulates across the whole order.

Aspect Ratio Limits for Reliability

Aspect ratio for a microvia is the dielectric depth divided by the drilled diameter, and it should normally stay below about one to one for a stacked build. Beyond that the plating at the bottom thins, the fill traps voids, and the barrel is left with a weak point exactly where the stress is highest. Keeping the ratio low is a design decision, not a process adjustment.

Where the layer has to be thick, the answer is usually an offset or staggered build, or a change of material rather than a push on the drilling parameters. Current density through the structure should also be assessed, because a stack carries the whole current of the net through a very small cross section, and the electromigration limits that apply to fine lines apply with more force here.

Thermal Cycling and Interconnect Stress

Reliability is proven by cycling, either through thermal shock, thermal cycling or an interconnect stress test. The test should reproduce the conditions the product will meet, and the acceptance point should be the number of cycles without a resistance rise rather than a visual inspection of a cross section.

Where coupons are used they should travel with the production panel and be built to the same stack, because a coupon that uses a different dielectric or a different fill is not evidence about the product. The IPC test methods for HDI structures describe how those coupons should be designed and evaluated.

Cross Sectioning, Coupons and Records

Cross sectioning remains the direct way to see the barrel, the fill and the interface between vias. Sections should be taken from a coupon that contains a representative stacked via, not from a corner of scrap, and they should be photographed at a magnification that shows the plating thickness across the wall.

Records should tie the section, the coupon and the panel serial number together, and they should include the plating thickness measured in the wall rather than only on the surface. Where the stack changes, the record has to be repeated, because a new fill chemistry or a new laminate outgassing profile changes the structure even when the drawing does not.

Repair Limits for HDI Builds

Repair on a stacked via is limited. There is usually no room to replace a via without disturbing the layers above it, and the heat needed to rework a stack can damage the fill and the surrounding dielectric. Repair limits should therefore be written into the documentation before the order starts, not discussed after a defect is found.

A practical rule is to allow conductor repair on the outer layer where the stack is untouched, and to scrap the unit where the defect is inside the stack. That rule keeps the decision out of the hands of whoever happens to be on shift, and it gives the process engineer a clear signal that the stack itself needs attention.

FAQ

Why stack vias instead of staggering them? Stacking frees routing area on every layer and gives the shortest possible vertical connection, which matters around dense ball grid arrays. Staggering is easier to build and to inspect, so it remains the better choice where the escape does not need the extra room and the build is already at the limit of the shop’s registration capability.

What causes a void inside a stacked via? Voids come from paste fill that shrinks during cure, from plating that closes over an opening before the interior is filled, or from a dimple that traps air when the next dielectric layer is laminated. All three are process related, and all three show up in cross section long before they appear as an electrical failure in the field.

Is copper fill better than paste fill? Copper fill gives a solid metal path, better thermal transfer and a flatter surface, which suits reliable stacked structures. Paste fill is quicker and cheaper, and it can be acceptable where the stack is short and the thermal load is low. The choice should follow the cycling requirement rather than the price of the material.