Switch Silicon and the PCB: Why a 4.8 Billion Yuan Bet Matters

On 31 August 2026, Chinese switch chip developer Centec Networks disclosed a private placement plan to raise up to 4.805 billion yuan, with the entire amount directed at research and industrialisation of next-generation high-performance switch silicon. Switch chips are the central hub of data centre networking, and as AI infrastructure expands, 112G and 224G signalling becomes mainstream and network bandwidth requirements rise accordingly.

The announcement is about semiconductors, but its consequences extend to board manufacturing. When a core device moves into domestic production and volume validation, the boards that carry it must be validated alongside it. Switch line cards, network interface cards, backplanes, power boards, and the complete assembled system all need a supply chain that can keep pace.

Why Boards Follow Silicon

A switch chip does not operate in isolation. Its performance depends on the environment the board provides: the impedance of every channel leaving the package, the loss of the dielectric those channels pass through, the quality of every via they traverse, and the stability of the power it consumes.

As SerDes rates move from 56G through 112G toward 224G, the number of channels per board, the port density, and the instantaneous throughput all rise together. The PCB stops being a passive carrier and becomes an active element of the signal chain. Stackup structure, dielectric loss, copper foil roughness, via stub, and reference plane continuity each consume a portion of the link budget, and the sum decides whether a port closes at its target rate.

This is why a domestic switch chip programme inevitably pulls the high-speed board supply chain with it. The chip cannot be validated without boards that meet its electrical requirements, and those boards cannot be sourced without a manufacturer that has already developed the relevant process capability.

What 224G SerDes Does to a Stackup

The progression in layer count is the visible part of the change. Boards of sixteen layers and above continue toward thirty, forty, and in the most complex AI server backplanes and switch cards, close to seventy-eight layers. But the layer count is a consequence rather than the goal; the goal is fitting the required routing, references, and power distribution into the available thickness.

Several material and geometry decisions follow.

Dielectric loss. At 224G rates, attenuation over the length of a backplane channel is dominated by the dielectric. Low-loss laminates in the M7, M8 and higher classes become necessary, and with them the process adjustments those materials require, from drilling parameters to press cycles.

Conductor loss and foil roughness. At high frequency, current concentrates near the conductor surface, so copper roughness increases effective resistance and therefore loss. Low-profile foils reduce this contribution, but they change adhesion and etch behaviour, so the process window shifts with the material combination.

Via stub. The unused portion of a plated through hole behaves as a resonant stub that distorts high-speed channels. Back drilling removes it, adding a process step with its own depth accuracy requirement. On a seventy-eight-layer board with thousands of high-speed vias, controlling stub length consistently is a manufacturing discipline, not a one-off operation.

Impedance consistency. When differential impedance is held within a tight band, such as plus or minus five percent, every contributor matters: etched line width, dielectric thickness after lamination, copper thickness, and registration. Achieving that tolerance on a sample is a capability. Holding it in volume is a process.

Reference plane continuity. A high-speed channel requires an uninterrupted return path. Splitting a reference plane to accommodate power routing creates an impedance discontinuity and radiates. Managing that requires plane partitioning planned at the layout stage, with fabrication constraints known in advance rather than discovered after the design is released.

Escape Routing, HDI and Fine Lines

A modern switch chip presents a high input-output count in a large ball grid array package. Escaping those balls from the area under the package, through the surrounding layer structure, and out to the front panel connectors is a routing problem that grows faster than the pin count.

Two structural responses are common. HDI and any-layer interconnect provide microvias close to the package, freeing routing channels in the layers beneath. Where density is highest, mSAP processes producing lines at 0.075 mm and below create the additional capacity needed in localised regions.

Both move the manufacturing requirement upward. Microvia diameter, position accuracy, wall quality, and void-free copper filling decide whether the connections are reliable. Fine lines demand tighter exposure accuracy, better etch control, and inspection with enough resolution to verify what was produced. And because these structures sit inside a thick, high-layer-count board, layer-to-layer registration has to hold through multiple lamination cycles, with cumulative error staying inside the tolerance the outer layers require.

The practical consequence for a customer is that the board’s critical parameters should be confirmed against a manufacturer’s demonstrated capability before the design is frozen. A PCB capability statement covering achievable microvia size, minimum line width, aspect ratio for plated through holes, and impedance tolerance converts an assumption into a design input.

Power Integrity and Heat Arrive on the Same Board

High-speed switch silicon does not only need clean signal channels. As switch chip power and port density rise, power integrity and thermal management become equally binding constraints, and they have to be solved on the same substrate.

A high-performance switch draws large transient currents at low voltage. The power delivery network must present low impedance across a wide frequency range, which means a dense decoupling network, adequate plane capacitance, and short, low-inductance paths from capacitor to die. Localised heavy copper is often used to carry current in specific regions of the board.

That creates an unusual combination. The same board must carry low-loss, tightly controlled high-speed layers and heavy copper power layers, and the two have competing requirements. Heavy copper changes lamination behaviour and etched feature tolerance; low-loss materials behave differently under drilling and pressing. Reconciling them is more demanding than building either a pure high-frequency board or a pure heavy-copper board, and it is where the real manufacturing difficulty in switch hardware now sits. Those combined requirements are characteristic of AI infrastructure boards, and they are why fabrication process control at the PCB manufacturing stage determines system-level outcomes.

Thermal design follows the same logic. High-power switching devices concentrate heat, and the board must conduct it away without creating hot spots that stress neighbouring components or shift the electrical behaviour of nearby channels. Thermal vias, copper spreading, and placement decisions that separate heat sources from thermally sensitive devices belong in the board design, not in the enclosure design after the fact.

Co-Development: Why Timing Matters More Than Price

A switch chip travels a long path from design to volume: engineering validation, design validation, production validation, and full system verification. Each phase generates board revisions, and each revision has to be manufactured, assembled, and measured before the next decision can be made.

That timeline changes what a chip developer needs from a board supplier. A supplier that can participate early in stackup, impedance, via, and material reviews shortens the debug cycle, because the electrical behaviour of a new board is understood before the first measurement is taken. A supplier that can only quote from a finished design adds a round trip to each iteration.

This is where co-development becomes commercially significant. The larger the domestic switch chip programme becomes, the greater the requirement for local high-speed board validation and stable delivery. The same dynamic extends into 800G and 1.6T optical modules, where the switch chip determines how data is forwarded and the optical module determines how it crosses between racks, and both demand low-loss material, high-precision manufacturing, and consistent impedance control. What emerges is a coordinated chain running from silicon through board and optical module to the finished system.

The practical test of a supplier in this environment is not a lower quotation. It is whether they can be inside the loop while the design is still moving, and whether the boards they produce in volume behave the same way as the boards that were measured in the lab. Establishing that requires a defined verification chain, including assembly-level testing that confirms the high-speed device operates correctly once soldered to the board rather than merely checking the bare board. The manufacturing threshold for switch hardware has moved from whether the board passes its specification to whether the system, with its switch silicon attached, runs stably in a data centre for years.

Frequently Asked Questions

Why does switch chip development affect PCB manufacturing? The chip’s performance depends on board-level parameters such as impedance, dielectric loss, via stub, and reference plane continuity. Higher SerDes rates tighten all of them, so the board becomes part of the signal chain rather than a passive carrier.

How many layers do switch boards require? Line cards and backplanes commonly sit above sixteen layers, with complex AI server and switch designs reaching thirty, forty, or close to seventy-eight layers for the largest backplanes.

What is back drilling for? It removes the unused portion of a plated through hole that extends past the signal layer, eliminating the stub that degrades high-speed channel performance at 112G and 224G rates.

Why do high-speed and heavy copper requirements conflict? Low-loss materials and fine geometry require one process window, while heavy copper changes lamination and etch behaviour. Combining both on one board demands tighter process control than either requirement alone.

What should a chip developer look for in a board partner? The ability to participate in stackup, impedance, and material reviews before layout is frozen, demonstrated capability on microvias and impedance tolerance, and a verification chain that covers the assembled board rather than the bare board alone.