Thermal Via Array Layout and Plugging Process Selection in High Power PCB Design

In high power PCB design, the thermal via array is not a simple stack of conductive holes. It is the core execution unit of the thermal management strategy. Its essence is to build a low thermal resistance path in the vertical direction of the PCB through copper column structures, efficiently conducting heat from the bottom pad of power devices such as MOSFETs, IGBTs, DrMOS, or synchronous rectifier ICs to inner layer copper planes and even to the heat dissipation copper foil or metal substrate on the back of the PCB. In a typical application, a single TO-220 packaged 650 V SiC MOSFET can reach a junction temperature of 135 degrees Celsius under 10 A continuous conduction. If a reasonable thermal path is not configured, the pad temperature gradient may exceed 40 degrees Celsius per mm, leading to solder joint creep failure and parameter drift. At this time, the equivalent thermal resistance of the thermal via array, or Rth,via, must be controlled at 0.8 degrees Celsius per W or less to meet the JEDEC JESD51-2 steady-state thermal test requirements.

Quantitative Influence of Thermal Via Geometry Parameters on Thermal Resistance

The thermal conduction performance of thermal vias is jointly determined by diameter, depth, quantity, and copper thickness. According to Fourier’s law of heat conduction and the cylindrical copper column model, the axial thermal conduction resistance of a single copper-plated via can be approximated as Rth equals L divided by k times pi times r squared, where L is the copper column length, that is, PCB thickness, k is the thermal conductivity of copper at about 390 W per meter Kelvin, and r is the copper ring radius of the hole wall. Taking a 1.6 mm thick FR-4 board as an example: with 0.3 mm drilled hole, 0.55 mm pad, 18 micrometer base copper plus 2 electroplating passes with final copper thickness of 35 micrometers or more, the single via Rth is about 12.6 degrees Celsius per W. When the hole diameter is increased to 0.45 mm with a 0.7 mm pad, under the same copper thickness, Rth drops to about 6.3 degrees Celsius per W. It can be seen that a slight increase in hole diameter brings nearly double the improvement in thermal resistance. However, it should be noted that increasing the hole diameter will occupy wiring space and may reduce the thermal stress fatigue resistance of the hole wall copper layer. Measurements show that when the hole diameter is greater than 0.5 mm and the adjacent hole spacing is less than 1.2 mm, the microcrack occurrence rate caused by CTE mismatch during reflow soldering increases by 47 percent based on IPC-TM-650 2.6.27 accelerated aging data.

Topology Optimization Principles of Array Layout

Thermal vias should not simply be uniformly densely arranged. They must follow a heat flux density oriented layout. Taking an 80 A DrMOS in QFN-56 package as an example, its bottom exposed pad size is 7.5 by 7.5 mm, and four groups of parallel power transistors are integrated inside. Thermal simulation with ANSYS Icepak shows that the heat flux density in the central area of the chip reaches 12.5 W per square mm, while the four corner areas are less than 2.1 W per square mm. Based on this, a gradient density array should be used. The central area is arranged with 8 by 8, totaling 64, 0.4 mm holes with 0.8 mm spacing. Toward the edge, it transitions to 6 by 6 with 1.0 mm spacing and 4 by 4 with 1.3 mm spacing in a three-level distribution. This scheme reduces the center temperature rise of the pad by 9.3 degrees Celsius compared with a uniform 0.9 mm spacing layout across the entire area. At the same time, all vias must be fully connected to the bottom GND or Power plane. Thermal relief is prohibited. Otherwise, thermal resistance will increase by an additional 15 to 22 percent. Measurement of a certain 48 V and 20 A DC-DC module shows that after canceling thermal relief, the MOSFET pad temperature rise dropped from 108 to 91 degrees Celsius at 25 degrees Celsius ambient and 100 percent load.

Dual Constraints of Plugging Process on Thermal Performance and Reliability

Whether thermal vias are plugged directly affects thermal conduction efficiency and long-term reliability. Open via has the lowest cost but has three major risks. First, during reflow soldering, solder paste is sucked into the inner layers through the holes, causing increased void rate in the pad. IPC-A-610 Class 2 standard requires voids of 25 percent or less, while measured open via designs often reach 35 to 42 percent. Second, residual flux in the holes corrodes the copper wall and accelerates ion migration. Third, microvia cracks are easily formed under mechanical stress. In contrast, epoxy fill plus planarization process can achieve 100 percent copper filling in the holes, reducing thermal resistance by 31 percent compared with open via and meeting IPC-6012 Class 3 high reliability requirements. However, the CTE of the plugging resin must be strictly controlled, preferably less than 45 ppm per degree Celsius, to match copper. Otherwise, the delamination rate of the filling interface after 500 temperature cycles from minus 40 to 125 degrees Celsius reaches 12 percent. The current mainstream solution uses copper paste fill. First, inject nano copper particle paste, then cure at 180 degrees Celsius and perform secondary electroplating, making the copper column continuity in the hole reach 99.7 percent. Measured thermal resistance is stable at 0.52 degrees Celsius per W with 0.35 mm hole diameter and 1.6 mm board thickness.

Collaborative Design with PCB Stack-Up and Reference Planes

The effectiveness of thermal vias is highly dependent on the characteristics of the reference plane to which they are connected. In a 4-layer board, if the power device is placed on the top layer and only connected to the second layer GND plane through thermal vias, because the GND plane copper thickness is usually 35 micrometers, its lateral heat diffusion capability is limited with in-plane thermal resistance of about 0.15 degrees Celsius per W per square cm, easily forming a heat island. The ideal solution is to use a 6-layer or 8-layer stack-up, setting the third layer as a 2 oz, or 70 micrometer, thick solid power plane such as minus 12 V or PGND, and the fourth layer as a 2 oz solid GND plane, and connecting both planes simultaneously through a double-layer thermal via array. At this time, heat flow can diffuse laterally along the two high thermal conductivity planes and then be led out to the housing or heat sink through multiple points. Measurement of a certain automotive OBC motherboard shows that a 6-layer board with 2 oz PWR and GND inner layers plus double-layer thermal vias reduces the MOSFET pad temperature rise by 22 degrees Celsius compared with a 4-layer board with 1 oz GND. In addition, high-speed signal traces are prohibited within 10 mm around thermal vias to avoid common mode noise coupling. Measurements show that when a USB 2.0 differential pair is less than 8 mm from the thermal via array, radiated emission exceeds the limit by 6.2 dB microvolts per meter at 125 MHz.

DFM Verification and Mass Production Feasibility Check

Thermal via design must pass design for manufacturability closed-loop verification. Key inspection items include: first, minimum annular ring of 0.15 mm or more for 0.3 mm drilled holes; second, hole edge distance from copper foil edge of 0.2 mm or more to prevent ring breakage caused by etching undercut; third, the total number of thermal vias on the same network must not exceed the single drilling machine capacity of the PCB factory, with mainstream equipment limited to 32,000 holes per board; fourth, the plugging process requires confirmation of the supplier’s filling yield, requiring 99.95 percent or more per IPC-A-600G Class 3. A certain 3 kW server power PCB once arranged 37,500 thermal vias under a single SiC module because it ignored the third item, causing the drilling process to exceed time by 37 percent. Finally, by changing some holes from 0.35 mm to 0.4 mm and optimizing array density, the total number was reduced to 28,600, meeting the mass production takt time requirement. The final mass production board, after 1,000 thermal shock cycles from minus 55 to 150 degrees Celsius, maintained shear strength of all thermal vias at more than 25 N per IPC-TM-650 2.4.21, with no delamination and no cracking.

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