High-Speed FPGA PCB Design: Stack-Up, Power and SerDes

A modern high-speed FPGA is not a component that gets placed on a board; it is a system that imposes requirements on everything around it. Transceiver lanes run at tens of gigabits per second, the device may present dozens of them, and the same package simultaneously drives a wide parallel memory bus and a high-current core supply. The design problem spans signal integrity, power integrity, thermal behaviour and manufacturability at once, and the decisions that matter most are taken before any routing begins.

Start From the Device Limits

Three numbers from the device documentation set the shape of the whole design: the maximum transceiver rate, the maximum transient current the core can demand, and the maximum junction temperature.

Transient current is the one most often underestimated. A large device can change its current demand in microseconds, and the resulting voltage excursion is the product of that change and the impedance of the supply path. If the path presents even a milliohm, a very large transient produces a dip large enough to consume the timing margin of the memory interface. That product is the reason the supply network is designed before the routing.

The designer also needs to know which supplies are sensitive to noise and which are merely high current. Core supplies are power-hungry and relatively tolerant; transceiver and phase-locked-loop supplies are much less tolerant and need to be separated from the switching noise of the rest of the board. Knowing this at the beginning is what allows the supplies to be arranged rather than patched.

Partition the Design by Speed

The practical first step in layout is to divide the board into zones by data rate: the high-speed zone containing serialiser/deserialiser lanes, optical module interfaces and the high-speed bus connectors; the medium-speed zone with the memory interfaces and low-voltage differential signalling; and the low-speed zone with general purpose I/O, configuration and maintenance interfaces.

The purpose of the division is to prevent a single uniform rule from being applied everywhere. Treating every net as if it needed the same care produces a design that is over-constrained where it does not matter and under-constrained where it does. Zones allow the strict requirements to be applied where they are needed and simple rules elsewhere, and they prevent high-speed routing from being shared with noisy switching nodes.

Stack-Up and Material

The stack-up is where the electrical requirements and the cost of the board meet. Three variables interact: the impedance target, the loss the channel can tolerate and the number of layers the design can afford.

The loss behaviour of the laminate sets the reach of the channel. Lower-loss materials allow longer traces at the same rate, or higher rates over the same trace. The stack-up typically uses those materials only where the signal quality demands it and standard materials elsewhere, in a hybrid construction with the high-speed layers on low-loss dielectric and power and general routing on conventional laminate.

Layer assignment follows several rules at once. Every high-speed trace should have a continuous reference plane adjacent to it, which usually means placing signal layers next to plane layers rather than next to each other. Power planes should be close to the ground plane that references them, so that the plane pair forms a low-impedance path over the frequency range that matters. And the total number of layers should be chosen so that routing does not force compromises; installing a layer costs less than routing a high-speed bus through a compromised reference.

The Power Delivery Network as a Radio Frequency Problem

Power distribution behaves like an RF circuit over the frequency range where the device draws its switching current. At low frequency, the regulator controls the voltage; at higher frequencies the regulator cannot respond and the local capacitance supplies the current; at the highest frequencies only the plane capacitance and the package itself are fast enough. The power delivery network is designed so that all three work together across the whole band.

Some of the supplies need to be separated entirely. Transceiver rails and clock supplies benefit from their own regulation and from isolation between them and the digital supply, so that switching noise does not arrive through the supply. Power islands, dedicated regulators and filtering components placed at the boundary are the usual methods.

Decoupling as Layers of Capacitance

The capacitors in a decoupling scheme are not interchangeable, and arranging them by value without regard to frequency produces resonances rather than suppression. A working arrangement has three layers.

The bulk capacitors handle the low-frequency content and the energy storage the regulator needs time to supply. They sit near the supply entry point, where their size does not create a placement problem.

Mid-value capacitors handle the middle of the band and sit close to the device, under the package footprint if the board allows, where their distance still contributes negligible inductance.

The small high-frequency capacitors are placed within a millimetre or two of the balls they serve, because at high frequency the trace to the capacitor is a significant impedance. Their count is high and their value is small, and their purpose is to supply the fastest transient current.

Where the design has room in the stack, a thin high-permittivity core can be embedded between a power plane and a ground plane to add capacitance across the board. This supplies the top of the band where discrete capacitors cannot respond, and it reduces the number of small capacitors the design otherwise needs.

Target Impedance and Simulation

The supply network has a specified impedance it must stay below across the frequency band, and that number comes from the largest acceptable transient ripple divided by the current step the device can produce. Designing to that number is a simulation exercise, not a rule of thumb: sweep the network from the low kilohertz into the high megahertz range, examine the impedance curve for resonances, and add capacitance at the frequencies where it peaks.

A resonance in the curve is the signature of capacitors or plane structures interacting, and it is corrected by adding a component whose self-resonance falls at that frequency rather than by adding more of a value already present. The same model also shows whether the supply path has become an emitter, since a resonant structure radiates as well as it decouples.

Differential Pair Routing: Equal Time, Not Equal Length

The requirement that matters is that both conductors of a differential pair arrive at the same time. Equal physical length is only an approximation of that, and it is wrong whenever the two conductors run on different layers.

Signals propagate at different speeds on outer layers, which are partly exposed, and inner layers, which are surrounded by dielectric. A pair that changes layer mid-route therefore needs its length compensation recalculated by propagation delay, not by measured length. This is the reason a design can pass a length-matching check and still fail a common-mode measurement.

Two other details belong with the pair. Both conductors should change layer through mirrored via structures rather than through independent ones, because an asymmetric pair of vias converts part of the differential signal into a common-mode signal. And the pair should keep a continuous reference plane beneath it, since a route that crosses a plane split interrupts the return path and damages the channel in a way that no amount of length matching will repair.

SerDes Channels and Stub Control

A long channel is judged by the loss it presents at the Nyquist frequency and by the reflections it returns. The dominant non-ideal element in a through-hole channel is the unused portion of the via barrel below the layer where the signal enters: the stub.

The stub behaves as an unterminated transmission line, and at high rates it resonates within the band the channel is using. The correction is back-drilling, in which the unused barrel is reamed away from the far side after plating. The depth control is the critical parameter, because drilling too deep damages the connection and drilling too shallow leaves the stub that the process exists to remove. The rule is expressed as a maximum remaining stub length, which becomes tighter as the data rate rises, and the tolerance the fabricator can hold is a question to settle before layout rather than after.

Memory Interfaces and Timing

The parallel memory interface has its own constraints, and they are about groups rather than individual traces. Address and command signals are routed in a topology that reaches each device in turn, with a defined length relationship between the group and the clock, and each byte lane’s data signals are matched among themselves. The exact windows are narrower than intuition suggests on a wide bus, because the signals that are compared against each other are travelling together.

What protects the design is not only the geometry but the training the controller performs at power-up. The trace relationships have to be inside the range the training algorithm can correct, which is a constraint on the design and a reason to simulate the interface rather than only to match lengths.

EMC and Thermal as Design Inputs

Two subjects are habitually postponed to the end and both are cheaper when handled as design decisions.

For emissions, the high-speed region can be enclosed by a via fence that ties the reference planes together around it, and interface traces can be referenced closely to a plane as they leave the connector, which reduces the common-mode current they can excite. Both are layout choices, not add-on shielding.

For thermal, the arithmetic is unavoidable: a core supply delivering a large current at a low voltage dissipates a substantial power in a package whose junction temperature is limited. The path from junction to ambient has to be designed with copper on the board, thermal vias under the package and a defined interface to the heatsink. Adding that structure afterwards usually means losing board area that the routing has already used.

Both subjects also feed back into the routing: keeping the clock and power structures away from the board edges, and leaving clearance around the package for the thermal solution.

Manufacturability and Test

High pin count devices impose manufacturing constraints that should be checked before layout rather than after. The pitch of the ball array determines the smallest via and the diameter of the annular ring the fabricator must hold, and the routing density that results determines whether the layer count assumed in the stack-up is achievable.

Testability is designed in as well. Loopback structures at the transceiver lanes allow the channel to be exercised without an external partner, and they cost a small amount of board area at implementation time. A configuration chain kept short and routed with attention to signal quality allows the device to be programmed reliably in production. Both are difficult to add to a finished layout.

Where these subjects interact — the impedance of a trace or a via, the reference plane beneath it, the loss introduced by the medium — the tools of analysis are the same ones used elsewhere on the board. The behaviour of a reflection at an impedance change is described in the note on the reflection coefficient and impedance, the supply arrangements in more detail in the guide to power delivery system design, and the way controlled impedance is specified and verified in the article on the impedance control flow.

FAQ

When does an FPGA design need a low-loss laminate? When the channel loss at the operating rate approaches the budget the link can tolerate. Below that point a conventional laminate with a hybrid stack-up usually meets the requirement at lower cost.

Why is equal length not enough for a differential pair? Because the two conductors propagate at different speeds when they are on different layers. The compensation has to be calculated from delay, not from measured length.

What does back-drilling correct? The unterminated via stub left below the signal layer. It is drilled away from the opposite side to remove the resonance the stub would otherwise create.