Power Delivery System Design for High-Speed PCBs
Supply voltages keep falling and supply currents keep rising. When a core moved from a 130 nm process to a 90 nm process, the rail that had been comfortable at a higher voltage was expected to run near 1.2 V, with a larger current through the same package. The noise budget that the device can tolerate shrinks at the same time, so the power delivery system has moved from a detail at the end of a design to a subject that is analysed and simulated like any high-speed interface.
Two Questions, DC and AC
The same structure is examined in two ways, and each has its own observable. In the DC analysis the question is how much voltage is lost between the regulator and the device pin, which is the IR drop calculation. In the AC analysis the question is how the impedance between the power and ground planes behaves across frequency, which is the input impedance of the pair.
The two are linked. A plane that is too narrow raises the DC resistance and lowers the AC admittance at the same time, and both effects push noise into the device. This is also why the same four design variables appear in every discussion of the subject: the layer stack-up, the shape and extent of the power plane, the placement of the components, and the distribution of the vias and pins that connect the planes to the devices.
Why Input Impedance Is the Useful Measurement
The impedance seen between a power plane and its reference plane is a single quantity that summarises most of what can go wrong. Where the impedance is low, a switching current produces a small voltage disturbance. Where the impedance peaks, the same current produces a disturbance large enough to reach the device and to radiate from the board edge.
The most common use of that measurement is to evaluate where the decoupling capacitor population should sit. Every capacitor has a self-resonant frequency, and the impedance of the plane pair has its own resonances set by its dimensions and by the dielectric between the planes. Placing capacitors so that they damp those plane resonances flattens the impedance curve, and a flat curve means less noise generated inside the board and less energy reaching the board edge where it would become an EMC problem.
That is the practical argument for treating the capacitor layout as a system decision. A capacitor placed at the wrong location, or with a long via and trace loop, contributes its capacitance but not its damping, because the inductance between the capacitor and the plane pair dominates the impedance at the frequencies that matter. Placing a larger number of small devices close to the load, with short connections to the planes, is generally more effective than adding a large bulk device at the far end of the board.
The Three Subsystems
A working power delivery system is really three structures in series, and the noise has to pass through all of them before it reaches the transistor.
The first is inside the chip, where the supply distribution is built as a set of alternating metal layers. One layer carries strips running in one direction, the next layer carries strips running at right angles, and vias stitch the crossings together into a mesh. On a high-performance device the core and the I/O sections both include a significant number of decoupling cells built into the die, which act as the first line of defence because they are closest to the switching circuits.
The second is the package. Functionally it is a small PCB, with several power and ground planes of complex shape, and its upper surface usually carries positions for decoupling capacitors. The path from the die to the package floor is through bond wires or through bump connections, and both contribute inductance that the on-die decoupling cannot remove.
The third is the board itself, which carries a large continuous power plane and a matching ground plane, a population of discrete decoupling capacitors of several values, and the regulator module that feeds the whole rail.
Bond wires, bumps and solder balls join the three together. The design intent is simple: every device on the board should see a supply that stays inside its tolerance. What makes it difficult is that the switching currents are large and fast, and the parasitic elements of the structures that carry them have their own high-frequency behaviour, so the voltage at the device is not the voltage at the regulator.
What Raises the Impedance
The designer has a limited set of levers, and almost all of them act on geometry.
A narrow neck in a plane raises both the resistance and the inductance of the path. A plane that is perforated by a dense field of via antipads loses copper area, and the current has to flow around each opening. A plane that is split by an unrelated signal route forces the return current to detour, and the detour is a larger loop area with more inductance. These are not exotic errors; they are the normal result of routing a busy board without a plan for the plane shapes.
Via and pin distribution has a similar effect at a smaller scale. A device with twenty supply pins is not helped by tying all of them to a plane through two vias in one corner, because the current has to spread through a thin copper sheet to reach the far pins. Distributing the vias across the pad field shortens the distance the current travels in the plane, which is the reason supply pin escape patterns are planned as carefully as signal escapes.
Stack-Up and Plane Shape
The stack-up sets the raw material of the power delivery system. A thin dielectric between a power plane and a ground plane gives a high plane capacitance and a low impedance at high frequency, which is a free benefit that costs only the choice of the prepreg and core thicknesses. A stack that places the planes deep in the board, far from the components, gives up that benefit and forces the decoupling to be carried further by discrete parts.
The shape of the plane matters too. A wide, uninterrupted plane behaves like a transmission line with a low impedance, whereas a plane that is squeezed into an irregular outline has local regions of high impedance that will show up as noise on the devices sitting above them. When a plane must be split, the split should follow the boundary between quiet and noisy circuits rather than an arbitrary grid line, and no high-speed signal should cross it.
Working the Design in Order
The order that works is to define the stack-up first, then the plane shapes, then the capacitor placement, and to check the result rather than to assume it. A DC analysis of the rail confirms the IR drop from the regulator to the furthest pin. An AC analysis of the plane pair shows whether the resonances are damped. Both are cheap once the stack is defined and expensive to correct after the artwork is released.
That check is also part of what an assembly partner needs to understand before quoting a build, because the stack-up decisions carry into the material list and the drilling programme. Our PCB capabilities page describes the layer counts and dielectric options we routinely build, and it is worth reading it while the stack is still a spreadsheet rather than a finished drawing.
Once the design is fixed, the assembly side has its own constraints to respect. A dense decoupling population around a large processor changes the paste and reflow profile locally, because the copper under the capacitors is connected to planes that act as a heat sink. Parts with different thermal mass placed side by side need a profile that satisfies both. Our SMT PCB assembly process reviews those areas before the first build rather than after the first defect report.
Cost, Not Just Noise
A design engineer has to balance the electrical requirement against the cost of meeting it. Every additional plane layer, every additional capacitor part number and every additional via adds to the cost of the board, and the optimisation is not the same for a high-volume consumer product as for an instrument built in the hundreds.
The useful discipline is to decide the noise target first, because the target determines the stack-up and the capacitor population and everything else follows. A rail that has to stay within a few tens of millivolts needs the thin plane pair and the distributed capacitors. A rail that can tolerate a wider band can be served by a simpler structure, and the savings can be put into the parts of the design that affect the product more.
Reading the impedance curve and knowing which peak causes the problem is the skill worth building, because it turns the argument about capacitor population into a measurement. The same analysis applies from the prototype through to volume production, and it is one of the reviews we run with customers during turnkey PCB assembly projects where the design and the build are handled as one programme.
FAQ
How much IR drop is acceptable? It depends on the rail tolerance, but a common working target is a few percent of the nominal voltage from the regulator to the furthest load pin, with the budget shared between the plane resistance and the connector or cable resistance.
Why not just add more decoupling capacitors? Because the capacitor only helps where it is connected. Above the self-resonant frequency of the part and its mounting loop, extra capacitance does not lower the impedance, so the placement and the via geometry matter more than the count.
Can a power plane be split to isolate a noisy circuit? Yes, but the split has to be placed so that no signal crosses it and no return current is forced to detour around it, otherwise the isolation creates a worse problem than the one it solves.
