Via to Trace Clearance: The Clearance Rules Multilayer PCBs Need

Routing a multilayer board is mostly an exercise in deciding where copper belongs. Traces carry the signal, planes carry the return current, and vias stitch the two together. What gets far less attention is the space that must be left around a via before the board ever reaches the drill. When that space is too thin, the fabricator sends back the familiar message: the hole is too close to the trace. Nothing on the schematic is wrong, the netlist is correct, and the board is still unbuildable at the quoted price point. Understanding via to trace clearance is therefore not an academic exercise. It decides whether a design quotes at a normal price or comes back with a surcharge, and whether the finished product survives its warranty period.

What the Fabricator Actually Measures

When a fabricator reviews a design, the check is not simply the distance a designer drew. It is the space between the finished hole wall and the nearest copper of a different net, calculated after every downstream process has moved something. Three quantities feed into that number: the drilled hole diameter including its tolerance, the pad diameter as it will exist after CAM has finished optimising the artwork, and the positional accuracy of the drill and the lamination press. A drawing that shows a comfortable 6 mil gap between hole edge and trace edge can end up with almost nothing once the tolerance stack is applied.

The same issue appears on a different axis when two vias sit close to each other. The drill bit passes through material that has already been weakened by its neighbour. The result is uneven loading on the drill tip, uneven heat removal, and a breakage rate that climbs with via density. A broken bit does not merely cost a tool. It can tear the wall of the hole it was cutting, leave a ragged hole, or leave a via that never gets drilled at all, which passes visual inspection and fails electrical test much later.

Why High Density Layouts Trigger the Problem

Vias cluster where the routing is hardest, which is exactly where the copper is most congested. In a dense BGA escape region, a via may sit with traces of three different nets running past it in the layers above and below. Each of those traces wants its own clearance, and the sum of those clearances can exceed the space available on a coarse grid. Designers then push the via closer to one of the traces, and the violation appears.

Blind and buried structures make this worse because the drill depth changes the aspect ratio of the hole and the way the bit behaves. The rules that govern these structures are described in more detail in this discussion of HDI board CAM methods, where the interaction between via type and the drilling sequence is laid out for each class of stackup.

The CAM Engineer’s Answer: Shrink the Pad

Faced with a violation, a CAM engineer has a small number of options. The design cannot be re-routed at that stage, and the drill size is usually fixed by the required aspect ratio and current capacity, so the remaining variable is the pad. The engineer trims the pad on the offending side, which opens up the space to the neighbouring trace while leaving the rest of the pad intact.

This CAM pad reduction is a legitimate manufacturing practice, and every fab applies some amount of it. The problem is that the designer never sees it. A pad drawn at 20 mil can come back at 18 mil, and with an annular ring of 4 mil drawn, the trimmed side may be left with 3 mil of copper around the hole. If the drill then lands at the upper limit of its tolerance, that 3 mil can shrink to 1 mil, and a 1 mil ring is not a manufacturing feature, it is a lottery ticket.

The trimming is also directionless in the sense that it follows the violation. Two hundred vias on a board may each be trimmed on a different side, so the resulting copper distribution around the hole becomes irregular. There is no simple rule of thumb that tells a designer where the weakness will land.

Annular Ring Under Worst-Case Tolerance

The annular ring is the surviving copper between the hole wall and the edge of the pad. It is the feature that carries current between the via barrel and the trace, and it is the feature that mechanical stress acts on when the board flexes or when a connector is pressed home. A thin ring does not fail immediately. It passes continuity test, it passes flying probe, and it works in the first prototypes. The failure appears months later as an intermittent open on a board that has been in the field, and by then the root cause is buried under a conformal coating.

This is why the industry treats annular ring as a design input rather than a manufacturing detail. If the pad is sized on the drawing with enough margin that a CAM pad reduction plus a worst-case drill registration still leaves an acceptable ring, the via stops being a reliability risk. If the pad is sized to the minimum the fab will accept, the same via becomes a statistical defect generator.

Lamination Shift and Drill Registration

Drill registration describes how accurately the drilled hole lands relative to the copper features on each layer. It is a compound figure. The drill machine contributes its own positional tolerance, the panel may move during handling, and on multilayer boards the layers themselves move during lamination. A six-layer board made from two cores and copper foil pressed together can shift by up to 0.05 mm during the press cycle, and that shift is not uniform across the panel. It varies directionally, so a via near the panel edge may be offset in one direction while its neighbour is offset in another.

Lamination drift also affects the stackup as a whole. Designs that pair an unbalanced layer build with aggressive via clearance rules tend to produce panels with more warpage and more registration complaints, which is the subject of a separate discussion on balanced stackup and odd layer count. Choosing a symmetric build does not remove the requirement for clearance, but it does make the distribution of the error more predictable.

A Practical Clearance Table

The following values are the ones most fabs will build without argument on a standard FR-4 process. They describe the distance from the inner-layer hole edge to copper of a different net, and they should be applied as minimums on the drawing, not as targets to aim for.

For inner layers, four-layer boards are generally forgiving because the routing density is low; a designer may treat the inner-layer hole to copper clearance as non-critical. Six-layer boards should hold at least 6 mil. Eight-layer boards should hold 7 mil. Boards with ten layers or more should hold 8 mil.

For the distance between two inner hole edges, the requirement depends on whether the vias share a net. Vias of the same net can be placed as close as 8 mil or 0.2 mm apart. Vias belonging to different nets should be separated by at least 12 mil or 0.3 mm. These numbers assume the vias are connected to the same layer and that neither is in a region where the drill will be working at an extreme aspect ratio.

Design Rules That Keep the Violations Away

Most clearance violations are avoidable long before the layout is finished. Placing the power and ground via pattern early, before the signal routing begins, means the dense regions are defined by the person who understands the electrical requirement rather than discovered by the router afterwards. Keeping via pitches on a regular grid, even where the grid is coarse, gives the drill program a predictable pattern and reduces the chance of two holes landing in the same weak spot.

Designers should also check the pad stack against the fab’s capability before routing, not after. A pad stack that requires a 3 mil annular ring after trimming is a stack that only works on a perfect day. Sizing pads for a 5 mil or 6 mil ring costs a small amount of routing space and removes an entire class of reliability failure.

Finally, it is worth considering the copper around the via rather than just the clearance to it. An isolated via with a thin ring and no surrounding plane has nothing to distribute mechanical stress, and it offers no redundancy if the barrel develops a crack. Where the net allows, adding a short pour-connection or a wider pad at the via gives the structure more tolerance for the manufacturing variation that is guaranteed to occur. The prevention of defects that form during plating is covered further in this discussion of copper plating defects and their prevention, since plating quality and ring geometry interact closely.

FAQ

Why does my fab complain about holes being too close to traces when my DRC passes? Most DRC rules check the distance drawn in the database, using the pad size as designed. The fabricator checks the distance after tool compensation, pad trimming and worst-case drill registration. A design can pass DRC comfortably and still leave less than 3 mil of copper after the board is actually built.

How small an annular ring is safe on a multilayer board? Four mil is the common minimum for commercial work and 5 to 6 mil is a much better target when the design must survive thermal cycling or mechanical stress. Anything below 3 mil after all tolerance is applied should be considered a reliability risk rather than a manufacturing limit.

Can I specify that CAM must not trim my pads? You can ask, and some fabs will honour the request, but a design that depends on that answer has no margin. The better approach is to size the pads so that trimming is harmless and the layer count and via density are chosen so that the space exists in the first place.