Power Plane Splitting: Width Rules and Clearance Limits

Every multilayer board with more than one supply rail faces the same decision: whether to give each rail its own copper plane, or to share one plane and route the secondary rails as traces. The answer is not a matter of taste. Power plane splitting changes the impedance of the reference for every signal that crosses it, changes the thermal behaviour of the board, and changes what the fabricator must etch. Get it right and the board is quiet and cool. Get it wrong and the design develops intermittent faults that survive every bench test but appear in the field.

Start With the Small Rails

Small, low-current supplies are usually best handled in copper on a signal layer and then connected with traces that satisfy the current requirement. The reason is simple: a plane is a distributed structure, and a rail that draws a few tens of milliamps does not need the capacitance or the low impedance that a plane provides. Reserving plane area for it simply steals area from the rails that do.

Mid-voltage rails such as 12 V and 5 V deserve particular caution when they are the input to a switching supply. Those nodes are switching, so they carry high dV/dt content. If they must be split into a plane, avoid using that plane as the reference for important signals. The high-voltage swing couples into whatever references it, and the signal damage is often invisible until EMC testing.

Where a split power plane is used as a reference, give it to the module that actually uses that rail. If several rails are available, prefer the lowest voltage. A DDR3 module running from 1.5 V should reference the 1.5 V plane rather than the 3.3 V plane. In practice, DDR3 data lines usually reference the ground plane while address and control lines may reference the power plane, and that arrangement is deliberate.

Keep Power and Ground Adjacent

A power plane is only useful as a reference when it sits close to a ground plane. The thin dielectric between them forms the distributed capacitance that supplies high-frequency current to the devices on the board. If the layer directly beneath a power plane is a signal layer instead, that capacitance is lost, and the designer should compensate by adding generous ground copper and a dense pattern of ground vias on the signal layer.

The arrangement of layers around a split is therefore as important as the split itself. Adjacent layers that carry different power nets should not be placed so that they overlap, because the overlap creates a capacitor between two unrelated rails and couples noise from one to the other.

How Wide Should the Split Be

The plane split width, meaning the copper-free gap between two nets on the same layer, depends on the voltage difference across it. For analog and digital sections on the same board, a 25 mil gap is the usual recommendation. Between two digital rails, 15 mil is generally sufficient, and the width may be reduced locally where space is tight. The principle is that the gap should be as wide as the available area allows, because a wider gap reduces capacitive coupling across the boundary.

For the chassis or shield ground, the isolation gap should be at least 2 mm, and may be reduced locally but never below about 1 mm. Signals of any kind, including traces, vias and copper pours, should be kept clear of the chassis ground boundary.

One frequent mistake is to place a power via inside the isolation band. The band is free of copper by definition, so a via placed there has nothing to connect to and the net is broken. Checking the via placement against the split boundary is a mandatory review step, not an optional one, and the same tolerance arithmetic applies to the via to trace clearance around the boundary.

Creepage Distance and Voltage Classes

Creepage distance is the shortest path along the surface of the board between two conductors at different potentials, and it grows with voltage because the surface can track and carbonise under contamination. The working figures for coated and uncoated surfaces differ substantially, and both should be applied to the copper-to-copper spacing on the outer layers.

Below 24 V, a surface covered by solder mask requires a gap of at least 0.13 mm, while an exposed surface requires 0.64 mm. From 24 V to 48 V, the primary side needs 0.5 mm and the secondary side 0.2 mm. From 48 V to 100 V, the figure is 1 mm. From 100 V to 200 V it is 1.5 mm, from 200 V to 400 V it is 2.5 mm, from 400 V to 600 V it is 3.2 mm, and above 600 V it rises to 5 mm.

High-voltage and low-voltage sections should also be physically separated on the board, with as much distance between them as the layout allows, so that the switching node of a high-voltage rail cannot couple into a low-voltage signal or its reference. Where the design carries a switching supply, the layout of the regulator itself deserves the same attention as the planes; the techniques are described in this article on radiated EMI in switching regulator layout.

The 20H Rule and Edge Radiation

A power plane and the ground plane beneath it form a parallel-plate structure, and the fringing field at the edge of that structure radiates. The 20H rule addresses this directly: the edge of the power plane should be inset from the edge of the ground plane by at least twenty times the dielectric thickness between them, where H is that thickness. If the stackup gives 4 mil between the planes, the power plane edge should be at least 80 mil inside the ground plane edge.

In practice, more inset is better. The rule is a minimum, not an optimum, and a designer with spare area should pull the power plane further back. The effect is most significant on boards with fast switching supplies, where the RF energy coupled between the planes travels to the board edge and radiates from the exposed cross-section of the dielectric.

Return Paths and Split References

The single most damaging consequence of a split plane is the interruption of the return path. A signal travelling over a plane returns through the copper directly beneath it, and if the plane under the signal is split, the return current has to detour around the gap. The detour adds inductance, creates a radiating loop and turns the trace into an unintentional antenna.

When a split exists, no fast signal should cross it. A designer who must cross a split should provide a stitching capacitor or a via that carries the return current across the boundary, placed adjacent to the crossing. This is the same principle that governs traces routed along a board edge, which is covered in this discussion of ESD and PCB edge traces.

Ground splits deserve their own check for loops. A ground plane divided into islands that are joined only at one point can form a loop that acts as a magnetic pickup, and the cure is to ensure the split sections are connected where the return current actually flows, not merely where it is convenient.

Current Capacity and the Final Checks

Whatever arrangement the planes take, the copper must carry the current. A useful estimate for 1 oz copper is that 1 mm of trace width carries about 1 A on an outer layer and about 0.5 A on an inner layer. Plane connections must be sized the same way, and the via count through a plane connection has to be checked against the total current rather than the current of a single device.

The remaining checks are mostly about continuity. Confirm that the power path is not interrupted by a BGA via field or a dense high-speed bus, paying particular attention to 0.8 mm pitch BGA areas where the plane is perforated by hundreds of holes. Where a connector sits on the board edge, place a 10 mm to 20 mm band of protective ground with staggered double rows of vias tying every layer together, and verify that the isolation to chassis ground exceeds 4 mm where the design calls for it.

Finally, treat the plane review as a checklist rather than a judgement call. No signal crosses a split, no via falls in an isolation band, no two unrelated planes overlap, and the current path has been verified. A board that satisfies those four conditions will be quiet, and the ones that fail them will keep returning from the field.

FAQ

Should I split the power plane for every rail on the board? No. Only rails that carry significant current, or that feed a module whose signals reference that rail, justify their own plane area. Small rails are better handled in copper on a signal layer, which preserves plane area for the rails that need it.

What is the 20H rule and is it still relevant? The rule says the power plane edge should be inset from the ground plane edge by at least twenty times the plane separation, to reduce edge radiation from the fringing field. It remains relevant for boards with switching supplies and fast edges, and more inset than the 20H minimum is always preferable.

What happens when a high-speed signal crosses a split plane? The return current cannot follow the trace directly, so it detours around the gap. The detour increases loop inductance, raises emissions and degrades signal integrity. If a crossing is unavoidable, place a stitching capacitor or ground via near the crossing so the return current has a short path.