SDRAM Radiation: Layout Rules for External Memory

External memory is one of the most common sources of radiated emissions on a microcontroller board, and it is one of the most fixable. A parallel SDRAM bus runs at a high clock rate with fast edges, and its traces carry the same data on many lines at once. When a product fails a radiated emission measurement and the enclosure cannot be changed, the layout of that bus is where the solution has to be found. SDRAM radiation is not a mysterious phenomenon; it follows from loop area, reference plane continuity and trace topology.

Why the Memory Bus Radiates

SDRAM is clocked at a high frequency and its edges are fast, so it has to be treated as a high-speed transmission line rather than as a bundle of slow logic signals. Any distortion of those signals widens the radiated spectrum, which makes the emission worse and spreads it over a wider band. The two mechanisms that matter most are impedance discontinuity, which produces reflections, and return path interruption, which increases the loop area that acts as the antenna.

Shared pins make the problem harder. Where the memory controller shares address or data pins between SDRAM and flash, the routing topology becomes more complex, and the branches carry the same fast edges over longer paths. The result is a structure that radiates more efficiently than a simple point-to-point bus.

Signal Integrity First

The first group of measures is the standard high-speed discipline. A four-layer or higher stackup gives the bus a solid reference plane, and the characteristic impedance of the traces should be controlled at around 50 ohm. Vias should be kept to a minimum on the bus, because each one introduces an impedance discontinuity and creates a reflection. Trace spacing should follow the usual three-times-the-width rule so that coupling between adjacent lines does not add to the distortion.

Length is a design parameter as well. The memory should be placed as close to the controller as the mechanical layout allows, and the bus length kept short, typically under about 120 mm. Every additional millimetre adds loss and delay, and neither helps emission or timing.

Once the signal paths themselves are controlled, the next gain comes from the return path.

Return Path Continuity

At these frequencies the return current flows in the reference plane directly beneath the signal trace. If the plane is interrupted by a split, a slot or a layer change without a nearby reference, the return current must detour, and the loop area grows. That larger loop is what radiates.

Where a signal changes layers and the reference planes differ, a stitching capacitor or a ground via next to the transition restores the return path. This is particularly important where the memory bus crosses between a ground reference and a power reference, because the return current has to move between the two planes. Keeping the reference plane continuous under the entire bus is the simplest way to avoid the problem in the first place.

Routing the Clock on Inner Layers

The clock trace carries the strongest radiated level of any signal in the memory interface, because it switches at the highest rate with the most regular pattern. Two measures reduce its contribution. First, route the clock on an inner layer, where the copper of the outer layers screens the field. Second, surround that routing with ground copper connected to the reference plane, so the field is confined between the plane and the ground pour.

The same treatment is worthwhile for the rest of the bus when the design allows. Routing the SDRAM and flash signals on inner layers, with ground on both outer surfaces, uses the board as a shield rather than as an antenna, and it costs nothing beyond the layer count that the design already requires.

Distance From Other Structures

A long trace or a cable that runs close to the memory bus behaves as an antenna: it couples energy from the bus and radiates it. Keeping other signals and any cable attach points away from the memory routing is the first step. Where physical separation is not possible, a ferrite bead or a filter at the point where the long trace or cable connects attenuates the coupled energy before it leaves the board.

Connectors and cables deserve particular attention, because they are the structures that most efficiently convert board-level noise into radiated emission. The principles of EMI suppression applied at the interface are more effective than any measure taken in the middle of the board.

Taken together, these measures describe a layout method rather than a set of patches.

Practical Layout Sequence

Place the memory device first, close to the controller, and orient both so the bus runs directly between them. Define the stackup so that the bus layers have solid reference planes, and set the impedance target before routing. Route the clock on an inner layer with ground screening, then route the rest of the bus with consistent spacing and matched lengths within each group. Then check every layer transition for a return path, and add stitching where the reference changes.

This is the same discipline described for microcontroller core board design and for high-frequency trace and data bus routing in general. The measures are not specific to one memory part; they follow from the physics of fast edges on long conductors.

The board edge deserves a final look. A plane or a trace that extends to the edge of the panel radiates from that exposed edge, so keeping the copper pulled back from the outline reduces emission without any change to the circuit. The same reasoning applies to the region around the memory: leaving a quiet area with continuous ground beneath it gives the field somewhere harmless to terminate.

If the design has a spare layer, using it for a ground plane rather than for additional routing is usually the most cost-effective emission reduction available. It lowers the impedance of the return path everywhere, which helps every signal on the board at once.

Verification

Simulation can predict the reflection and coupling behaviour of the bus, but radiated emission is best confirmed by measurement. A near-field probe scan over the board identifies the regions that radiate most strongly, and comparing the scan before and after a layout change shows whether the change worked. Pre-compliance testing in a shielded room at the prototype stage is far cheaper than a redesign after a failed certification test.

The floorplan also affects how much of the emission the enclosure has to absorb. Keeping the memory interface toward the centre of the board, away from the edges and away from any opening in the chassis, reduces the field that escapes. This costs nothing at the design stage and can be the difference between a product that passes its radiated measurement with margin and one that needs a shield.

FAQ

How long should the SDRAM bus be? Keep it as short as the mechanical layout permits, typically under about 120 mm. Shorter traces reduce loss, delay and the loop area that radiates.

Why route the clock on an inner layer? The outer layers then act as a shield, and the field of the clock is confined between the plane and the screening copper. The clock has the strongest radiated level of any signal in the interface.

Does a stitching capacitor always fix a return path break? It restores a local return path when a signal crosses a plane split. It is a corrective measure, and a continuous reference plane is the better solution.