High-Speed PCB Layout: 20 Practical Questions Answered

High-speed layout questions come up again and again because the answers depend on frequency, geometry and the behaviour of the return current rather than on a fixed rule. The twenty points below are the ones engineers ask most often, answered as briefly as the physics allows. They are arranged from routing and vias through grounding, length matching, EMC and thermal design, and they assume a multilayer board with at least one continuous reference plane.

Routing high-frequency signals

Three things matter above anything else: impedance matching along the whole trace, physical separation from other signals, and the choice of transmission structure. For digital signals at high frequency, a differential pair is usually the better structure, because the two conductors reference each other and the common-mode noise they pick up tends to cancel. Impedance matching is not a single number either; it has to be held through the via transitions, the connector and the pad entry, not only along the straight run. The reference plane beneath the trace is part of the impedance, so a trace that crosses a plane split changes its impedance mid-flight and radiates.

Vias and electrical performance

More vias do affect a board, but the effect depends on frequency. For a low-frequency signal, a via is electrically almost invisible. For a high-frequency signal, every via adds capacitance, inductance and a stub, and the total should be minimized. If the routing does not fit because of the via count, adding layers is usually a better answer than stacking more vias in the same area, because a multilayer board gives each signal a plane to reference. Where a via is unavoidable in a high-speed path, keep the stub as short as the stack allows, and check the crosstalk spacing between the via and its neighbours.

Decoupling capacitors

More capacitors are not automatically better. What matters is the placement and the value. A capacitor is most effective when it sits at the supply pin of the device it is protecting, because the loop from the capacitor through the plane and back to the pin is what determines how well high-frequency noise is shunted. For an analog device, place the capacitor right at the supply pin, and use several values to address different frequency ranges; a single large capacitor has enough inductance to be ineffective at the frequencies where switching noise actually lives. Choosing a microstrip or stripline reference for the trace that carries the current completes the picture.

Through vias, blind vias and buried vias

Blind and buried vias are an effective way to raise density, reduce the layer count and shrink the board, and they reduce the number of through-holes that pass through the whole panel. They also cost more and demand tighter process control. Through vias are easier to produce and cheaper, so a conventional design should use them by default and reserve the other structures for the areas where density genuinely requires them.

Mixed analog and digital grounding

If the design carries high-frequency analog signals above about 20 MHz, in significant number and length, dedicate at least two layers to them: one signal layer and one large ground plane, with the signal layer stitched to ground by plenty of vias. That arrangement gives the analog signal a complete transmission medium with a matched impedance, isolates it from the digital signals by the plane itself, and keeps the return loop small because the ground is a plane rather than a trace. Where the ground is split, the return path of any signal that crosses the split becomes long and unpredictable, which is why the plane is preferred wherever the measurement accuracy justifies the layer cost. The trade-offs are discussed under ground routing and power trace planning.

Placing the regulator

When the input connector is at one edge and the processor at the other, the question is whether to put the regulator near the connector or near the load. If the input is an analog signal, keep the supply away from the analog section and pay attention to the noise performance of the regulator itself. For high-precision designs, separate the analog supply from the digital supply rather than sharing one rail, and route the digital supply so that it disturbs the analog section as little as possible. A shared rail between analog and digital is generally not recommended, because it makes the board hard to debug and the noise coupling difficult to control.

Length matching and serpentine routing

Length matching matters when the skew between two signals has to stay below a defined fraction of the bit period. As a limit, a length difference equal to half a wavelength produces a 180-degree phase difference and complete cancellation, so the mismatch must stay well below that value. Serpentine routing is used for two different purposes. In some boards it deliberately adds inductance or tunes an impedance, but in a high-speed path it is normally there to add length, and the inductance it introduces phase-shifts the high-order harmonics of the rising edge and degrades signal quality. Keep the spacing between parallel serpentine segments at least twice the trace width, and remember that a faster edge is more sensitive to the distributed capacitance and inductance of the pattern. The rules are set out in more detail under serpentine routing and length matching.

EMC and EMI

Electromagnetic compatibility has to be considered from the moment placement begins, because device position, stack-up, critical interconnect routing and component selection all feed into it. Keep the clock generator away from connectors that face the outside world. Route high-speed signals on inner layers with a continuous reference, and match the characteristic impedance to reduce reflections. Choose devices with a slower slew rate where the timing budget allows, because a slower edge has less high-frequency content. Select the decoupling capacitors with their frequency response in mind, not only their capacitance. Keep the return current loop small, since loop area is what radiates. Where necessary, control the extent of high-frequency noise with a split ground, and choose the chassis ground connection points deliberately. Reviewing the result against the radiated EMI rules for switching regulators is a useful cross-check on any board that contains a converter.

Transmission lines, packages and layer allocation

The most important decision in a multilayer high-speed design is how signal, power, ground and control lines are allocated to layers. As a minimum, the analog signals and analog ground should have a dedicated layer, and the power supply should have its own. That allocation decides the reference plane under every trace and the impedance of every net. The choice between two, four and six layers follows from it: a multilayer board exists to provide a complete ground plane and enough routing layers, and for a processor driving external memory the decision should be based on the interface frequency rather than on the core clock. Where the interface runs fast, a complete ground plane is mandatory and the signals should be length-matched. Line width follows from impedance simulation at the operating frequency, power traces follow from current, and in a mixed-signal design the ground stops being a trace and becomes a plane so that the return resistance is as low as possible. On the thermal side, remember that components are the dominant heat source, followed by the board itself and then heat arriving from outside; the design goal is to reduce generation and improve dissipation through copper area and thermal vias.

FAQ

Should I always split the ground plane between analog and digital? There is no universal answer, and the device data sheet is the best guide. Some mixed-signal parts recommend a shared ground, others an isolated one with a single tie point. Follow the recommendation for the device you are using.

How many vias are too many in a high-speed path? Treat every via as a discontinuity and remove the ones the routing does not need. For a high-frequency net, reduce the via count and keep the stubs short; for a low-frequency net, vias have almost no effect.

Why is a minimum trace width not the right starting point at 300 MHz? At that frequency the trace is a transmission line, so its width has to come from an impedance calculation that includes the dielectric thickness and the distance to the reference plane. Current sets the width for power nets instead.