FPGA Transceiver Routing and Power Delivery

A high speed FPGA board design is a routing problem, and FPGA transceiver routing is the part of it that decides the layer count wrapped around a power problem. The device can implement almost any function, so the interfaces are whatever the product needs, and the board has to carry all of them out of a package with hundreds or thousands of balls. The order in which those decisions are made decides how much of the board can be routed at all.

FPGA Transceiver Routing Starts With Bank Planning

An FPGA has its input output pins organised into banks, and each bank has its own supply voltage and its own timing characteristics. Which bank a signal is assigned to therefore determines both its voltage level and its achievable speed.

Planning the banks is a task that has to happen before the schematic is finished, because it constraints everything downstream. Assigning interfaces to banks without regard to their physical location on the package guarantees a board that cannot be routed, no matter how much copper is added.

Pin Assignment and Physical Layout

The pin assignment should follow the physical position of the connectors and devices on the board. A memory bus that leaves the package on the far side from the memory devices has to cross the entire board, consuming layers and adding length.

The vendor tools can help by exporting pin constraints and by evaluating a proposed assignment against the layout, and using them early is far cheaper than discovering the problem in the routing. Where the assignment is fixed by the existing schematic, the board layout may have to be rearranged around the device rather than the reverse. Our layer assignment notes describe how the resulting layer count follows from the escape.

Power Delivery and Decoupling

An FPGA draws a large current that changes quickly, and the power delivery network has to supply it without the rail moving more than the device tolerates. The decoupling network is a distributed array of capacitors whose impedance, together with the planes, must stay low across the frequency range of the current demand.

The capacitors close to the package handle the fastest transients, and their placement matters more than their total capacitance. Bulk capacitors further away handle the slower changes, and the regulator handles the average. Designing the network as a whole, rather than adding capacitors until the rail looks quiet, is what makes the result predictable. Our applications processor article describes the same problem in a related device.

Transceiver Channels

High speed serial transceivers are the most demanding nets on the board. They are differential, they are impedance controlled, they have a defined loss budget and their routing must often be matched within a specified skew.

The escape from the package is usually the hardest part, because the channels are grouped and the pitch is fine. Reference planes must be continuous under the whole channel, and any transition between layers needs the return path handled at the same time. Where the channel runs through a connector or a cable, the loss of that element belongs in the budget. Our transmission line article covers the impedance reasoning.

Configuration and Debug Interfaces

The device needs to be configured at power up, and the interface that does it, with its associated memory, is part of the board design. It should be placed close to the device and, where possible, with the same attention to signal integrity as the main interfaces.

Debug access is the other requirement that is easy to defer. A JTAG header and a way to observe the configuration process are essential on a first prototype, and the space they occupy is trivial compared with the time lost without them. Our prototyping article lists the access that is worth designing in from the start.

Clock Distribution and Referencing

An FPGA design usually needs several clocks, and some interfaces require a defined phase relationship between them. Deriving them from a common source gives that relationship, but the distribution network then has to preserve it.

Clock traces should be treated as controlled impedance lines, matched where a relationship is required and kept away from noisy switching nodes. The reference for each clock should be a continuous plane, and the jitter added by any buffer in the path has to be accounted for. Our crystal and oscillator notes cover the source end of that chain.

Layer Count and Cost

FPGA boards are among the most expensive to design and to fabricate, and the layer count is usually the dominant term. It is driven by the escape from the package, the number of interfaces and the power distribution needs.

Reducing it usually means reducing the number of interfaces or accepting a slower speed for some of them, which is a product decision rather than a layout one. Where the layer count cannot be reduced, the design should at least avoid adding layers for convenience, because each one adds lamination cycles to the schedule. Our high layer count cost article describes where that money goes.

Designing the FPGA Board for Bring Up

A first FPGA board is brought up in stages: power first, then configuration, then the clock, then one interface at a time. The board should be designed so that each of those stages can be observed and, where necessary, worked around.

That means power rail test points, an accessible configuration interface, and the ability to hold the device in reset while the supplies are measured. None of these consume significant area, and each of them converts a debugging exercise into a measurement. Our PCB prototyping notes describe the general principle.

Thermal Considerations

A large FPGA dissipates a substantial amount of power in a package whose thermal path runs through the board and through the lid. The board contributes by spreading heat laterally through copper and by conducting it to whatever the board is mounted against.

Thermal vias beneath the package, connected to internal planes, are the standard method of getting heat out of the device footprint. Where the product has a heatsink, the mechanical path between the lid and the heatsink matters as much as the board, and the two must be designed together rather than sequentially. Our reliability notes describe how the resulting temperature feeds into the life calculation.

Where the design must accommodate several interfaces at different speeds, the slow ones should not inherit the constraints of the fast ones. Applying transceiver grade routing to a configuration interface wastes layers and effort, and keeping the fast rules where they are needed is what keeps the board affordable.

The same reasoning applies to the layer count. Every layer added for a marginal improvement in one interface is paid for on every unit, and it lengthens the schedule. Recording which interface drove each constraint makes that trade visible when the design is reviewed.

FAQ

Should the FPGA pin assignment be done before the schematic? It should be planned before the layout, and ideally in parallel with the schematic, because it depends on where the connected devices will physically sit.

How much decoupling does an FPGA need? Enough to keep the power delivery impedance low across the frequency range the device demands. The count follows from the calculation rather than from a rule of thumb.

Can transceivers be routed on any layer? They can be routed on any layer that has a continuous reference plane, provided the impedance and loss budgets are met along the whole path.