Impedance Discontinuity in PCBs: Causes and Manufacturing Control

Impedance discontinuity is the difference between the impedance the design intended and the impedance the signal encounters. A 50 ohm trace that measures 46 ohm at one point is not a small variation; the reflection it produces at multi gigabit rates is what closes eye diagrams and makes a link fail intermittently.

Discontinuities appear in two places. Some come from the design itself, where a pad, a via or a connector changes the local geometry. Others come from fabrication, where etching, plating and lamination move the cross section away from the target. Controlling both is what controlled impedance manufacturing means.

Where Discontinuities Come From

Any change in the cross section of the transmission path is a discontinuity: the trace width under a component pad, the barrel and pads of a via, the pin field of a connector, the gap between a trace and the plane beneath it, and the solder mask that sits over the copper without being in the model.

Time domain reflectometry shows these as bumps and dips along the line. Reading a TDR trace is the fastest way to attribute a problem: a rise in impedance usually means less copper than expected, while a drop means more copper, a capacitive pad or a nearby plane that the design did not account for.

Fabrication Variables That Move Impedance

Etching removes copper under the resist, and the amount removed depends on the copper thickness, the etch chemistry and the position of the trace on the panel. Isolated traces etch differently from dense arrays, which is why a coupon placed in a quiet area of the panel can measure differently from the product itself.

Lamination presses the dielectric to a thickness that varies with the resin content and the copper distribution of the layers. Prepreg flows away from copper heavy areas, so the dielectric under a trace can be thinner or thicker than the stackup drawing specifies, shifting impedance by several percent across a single panel.

Via Transitions, Stubs and Layer Changes

A via is a capacitance in series with an inductance. The pad and the barrel add capacitance, which lowers the local impedance, while the unused portion of the barrel adds a resonant stub that can be far more damaging at high frequency than the via itself.

Back drilling, or a move to blind vias, removes the stub, and the remaining discontinuity is usually compensated by adjusting the pad size or by adding a small inductance in the trace beside the via. Where a signal changes layers, the reference plane change also has to be handled with a return via, otherwise the return current takes a detour and the impedance change is far larger than the geometry suggests.

Connectors, Pads and Test Points

Connectors are the largest intentional discontinuity on most boards. The pin field is capacitive, the launch geometry is imperfect, and the transition from the board to the cable is rarely modelled by the connector vendor in the conditions the board presents.

Test points and probe pads have the same effect on a smaller scale. A pad added to a differential pair for a scope probe adds capacitance to one leg, and if it is placed asymmetrically it converts part of the differential signal into a common mode component that radiates.

<img src="https://www.gopcba.com/wp-content/uploads/2026/06/Sierra-Wireless.png" alt="Impedance test coupon on a production panel” />

Test Coupons, Verification and Design Rules

Controlled impedance is verified with coupons on the production panel, measured with a TDR, and the result is compared with the specification. The coupon should be representative: the same layer, the same copper weight and a trace density similar to the product, otherwise the measurement describes the coupon rather than the board.

The design rules that follow are straightforward. Keep the reference plane continuous under every controlled impedance trace, avoid unnecessary layer changes, compensate pads and vias rather than ignoring them, and state the impedance target with its tolerance on the fabrication drawing. gopcb fabricates controlled impedance boards with coupon based verification so the measured result can be compared with the number in the design.

Stackup, Simulation and Field Solvers

The impedance of a trace is decided by its width, its thickness, the dielectric constant and the distance to the reference plane. A field solver converts those into a number, but only if the inputs describe the board that will actually be built, including the resin rich layer beside the copper and the plating thickness inside the barrel of a via stub.

Most projects start from a fabricator supplied stackup rather than an idealised one, because the available prepreg and core combinations constrain what can be pressed. The simulation is then run against that stack, the trace widths are adjusted to hit the target impedance, and the resulting values are written into the fabrication drawing along with the tolerance that the design is prepared to accept.

Design Review Checklist

Before release, confirm that each controlled impedance net has a continuous reference plane, that the widths and the gaps in the layout match the stackup calculation, and that every via on those nets has its stub accounted for. Then check the pads: a component footprint that is wider than the line it connects to is a capacitive discontinuity whether the designer intended it or not.

Finally, confirm the verification route. State the impedance target and tolerance on the drawing, agree where the coupon will sit on the panel, and define what happens if the measurement falls outside the band. A number in a note that nobody measures is not a controlled impedance specification, it is a hope.

Related reading: PCB manufacturing tolerances, high frequency trace routing, microstrip and stripline routing, and trace width calculation.

Materials and the Limits of the Model

The dielectric constant of a laminate is not a single number. It varies with frequency, with temperature and, in woven glass materials, with position, because the resin and the glass have different values and the trace runs alternately over bundles and over the resin rich gaps between them. At high frequency that periodic variation shows up as a small reflection that no cross sectional model predicts.

Choosing a material with a tighter dielectric tolerance, or orienting the traces at an angle to the weave, reduces the effect. Where the design cannot tolerate the residual variation, the answer is usually to widen the tolerance budget elsewhere rather than to insist on a material that no fabricator can supply consistently at the required volume.

A useful habit is to keep a short list of every discontinuity the layout introduces deliberately, with the reason and the compensation recorded beside it. Pads narrowed to match the line, a ground return via beside every layer change, connectors selected with the board to cable transition in mind and test points placed symmetrically on a differential pair all belong on that list, and reviewing it before release catches most of the problems that a time domain reflectometer would otherwise reveal on the first prototype.

FAQ

How much impedance variation is acceptable? Plus or minus ten percent is a common specification for a single ended line, and plus or minus five percent for tight differential pairs. The right number comes from the link budget rather than from a default.

Can a discontinuity be repaired after fabrication? Not usually. The geometry is buried inside the board, so the correction happens in the design or in the process, not on the finished panel.

Why does the coupon read differently from the board? Because etching and lamination depend on the local copper density. A coupon on a sparse area of the panel is not etched or pressed under the same conditions as a dense product area.