Advanced HDI PCB Manufacturing: Stackups, Microvias and Yield

Advanced HDI PCB manufacturing takes the density of a standard high density interconnect board one step further. Instead of one buildup layer on each side of a core, an advanced build stacks several laser drilled layers, uses via-in-pad structures under fine pitch devices and holds line widths below 60 µm. Every additional step multiplies the process risk, so the design has to be planned around what the press, the laser and the plating line can actually hold.

What Separates Advanced HDI From Standard HDI

A conventional HDI board uses one buildup layer per side, described as 1+N+1. Advanced builds move to 2+N+2, 3+N+3 or any-layer structures in which microvias connect almost any pair of adjacent layers without a mechanical core. The distinguishing features are the number of sequential lamination cycles, the presence of stacked rather than staggered vias and the fine line capability required to escape dense area array packages.

The payoff is routing density under a 0.4 mm or 0.35 mm pitch ball grid array, shorter interconnect length for high speed channels and a smaller board footprint. The cost is a longer, more tightly controlled process chain.

Design Requirements That Drive the Process

Advanced HDI designs usually specify a minimum line width and spacing between 50 and 60 µm on outer layers, capture pads of at least 250 µm for laser drilled vias and dielectric layers of 60 to 80 µm per buildup step. Aspect ratio has to stay close to 1:1 for a microvia, because deeper holes cannot be plated reliably at that diameter.

Layer assignment also matters more than on a conventional board. Because each buildup step needs its own reference plane, the routing plan and the plane plan have to be developed together. A signal layer added without a nearby reference forces a redesign rather than a simple re-route. The comparison of blind and buried via structures is a useful starting point when the layer plan is still open.

Sequential Lamination Explained

Sequential lamination means that the panel is pressed, drilled, plated and imaged more than once. The first press creates the core, the microvias are formed on its outer faces, and the second press bonds the next buildup layers on top. A 2+N+2 structure therefore takes two lamination cycles after the core, and any-layer builds take as many cycles as they have buildup layers.

Each cycle adds heat history, shrinkage and handling risk. Copper distribution has to be balanced at every stage so the panel does not bow between presses, and registration targets are cumulative, which means small errors from the first cycle are carried into the second. This is the single biggest reason advanced HDI yield is lower than conventional multilayer yield.

Laser Drilling and Stacked Microvia Structures

Laser drilled vias stop on the copper of the target layer. Pad size, foil thickness and surface treatment all set the process window, and the energy has to be tuned so the dielectric is removed without damaging the pad beneath. Stacked microvias place one via directly on top of another and require the lower via to be fully filled and planarised before the next layer is laminated.

A poorly filled via leaves a dimple or a void that shows up as an open or a reliability failure after thermal cycling. Staggered structures avoid the filling requirement by offsetting the vias, but they consume routing area that the advanced design was trying to recover.

Copper Plating and Via Filling Control

Plating quality decides whether the board survives assembly. Blind microvias need a continuous, void-free copper deposit with adequate thickness at the bottom corner, which is where the current density is lowest and the deposit is thinnest. Bath chemistry, additive balance and current waveform all influence the result, and panels are normally checked by cross sectioning coupons from each lot. The process is described in more detail in the notes on electroplating and via filling for HDI.

Via-in-pad structures add a second requirement: after filling, the pad must be flat enough to print solder paste on. A dimple deeper than about 25 µm disturbs the paste release and produces voiding under the component.

Fine Line Imaging and Etching

Lines below 60 µm are formed with thin copper foil, laser direct imaging and a controlled etch that compensates for the lateral undercut. Etch compensation is applied per layer, and the finished line width is verified on a coupon rather than on a production panel. Impedance targets must be recalculated with the actual dielectric thickness of each buildup layer, because the nominal value and the pressed value rarely match exactly.

Surface treatment before imaging also matters. A roughened copper surface improves resist adhesion and reduces opens, at the cost of slightly higher insertion loss on high speed nets.

Inspection and Reliability Testing

Inspection for advanced HDI has to be layered through the process rather than applied at the end. Automated optical inspection after each imaging step, X-ray or cross section for microvia registration and impedance coupons for controlled nets are all standard. Thermal stress testing, and where required thermal cycling, exposes weak plating before the boards reach assembly.

The build record should list the actual dielectric thicknesses, the measured impedance, the microvia dimensions from a cross section and any deviation approved during manufacture. That record becomes the reference for the volume build and the first document to consult when a field failure appears. Data preparation for these builds follows the usual checks described in HDI CAM methods, with additional verification of the drill schedule and the fill map.

From Prototype to Volume Production

Advanced HDI panels are usually qualified with a small prototype run before any volume commitment. The prototype should use the exact stack, the exact laminate and the exact via structure planned for production, because a change of material between the two invalidates the qualification. Cycle time and yield data from the prototype are the basis for a realistic volume schedule. gopcb reviews the prototype results against the production plan before the stack is released.

Material Selection for Advanced HDI

The laminate has to survive several press cycles without drifting out of tolerance, so advanced builds normally use high glass transition temperature material with a decomposition temperature above 340 °C. Resin flow behaviour matters as much as the electrical data: a buildup layer that flows too freely leaves thin dielectric over the microvia shoulders, while a stiff material can fail to fill the cavity around heavy copper.

Low loss grades are selected only when the channel loss budget demands them, because they narrow the press window and raise the price of every layer in the stack. Whichever material is chosen, the datasheet values for dielectric constant and thickness after pressing should be used for the impedance calculation rather than the nominal figures from the catalogue.

FAQ

How many layers can an advanced HDI board reach? The layer count itself is not the limit; the number of sequential lamination cycles is. Builds with three or four buildup steps per side are produced routinely, and the practical ceiling depends on the fabricator’s registration and plating capability.

Is advanced HDI necessary for every high speed design? No. Many high speed boards are built on conventional multilayer stacks with well controlled impedance. Advanced HDI is justified when the package pitch, the board area or the channel length cannot be solved any other way.

What is the hardest step in the process? Stacked microvia filling followed by planarisation. A void or dimple at that point cannot be repaired later, and it shows up as a reliability failure only after the assembly has been through thermal cycling.