Controlled Impedance PCB: Principles and Stack-Up Design
Controlled impedance means that a trace has a defined characteristic impedance and that the board is built to keep it there. It is one of the few requirements in printed circuit design that cannot be satisfied by the layout alone, because it depends on the dielectric thickness and the dielectric constant, which are properties of the stack-up that the fabricator produces. Understanding the relationship between the two is what allows a designer to specify an impedance that can actually be held rather than a number that looks good on a drawing.
What Characteristic Impedance Is
A trace carrying a fast edge behaves as a transmission line. Its characteristic impedance is set by the geometry of the trace and the material around it: the width of the conductor, the thickness of the dielectric beneath it, the dielectric constant of that material and, for a differential pair, the spacing between the two conductors as well. For a microstrip on the outer layer the solder mask also contributes, because it is part of the dielectric above the trace.
When the impedance of the trace and the impedance of the load do not match, part of the signal reflects back toward the source. At low speed the reflection settles before the receiver samples. At high speed the reflection arrives while the data is still being read, and it either closes the eye or, where the link is a clock, adds jitter. That is why controlled impedance becomes a requirement rather than a refinement once the rise time of the signal is short compared with the length of the trace.
Single Ended and Differential
A single ended line is referenced to a ground plane and is usually specified at fifty ohms, a value that is a compromise between loss, which falls as impedance rises, and noise immunity, which improves as impedance falls. Most radio frequency traces and many clock lines use it.
A differential pair carries the signal on two conductors that are driven with opposite polarity and, ideally, with no reference to anything else. Because the receiver looks at the difference between them, noise that couples equally onto both conductors cancels, which is why differential signalling is used for USB, Ethernet, PCI Express and the sensor interfaces described in our imaging system article. The differential impedance is set by the geometry of the pair and by the spacing between the two conductors, and it is usually specified at eighty five, ninety or one hundred ohms depending on the standard.
How the Stack-Up Determines the Width
For a given impedance the trace width is determined by the dielectric thickness and the dielectric constant. A thin dielectric between the trace and the plane means the field is concentrated and the impedance falls, so a thinner dielectric requires a narrower trace for the same impedance. A higher dielectric constant has the same effect.
That relationship is what makes the stack-up a design document rather than a manufacturing detail. Once the layer thicknesses and the materials are fixed, the trace widths follow, and they cannot be adjusted afterwards without changing the impedance. It is also why a material substitution breaks an impedance calculation even when the nominal thickness is unchanged, and why the calculation is repeated whenever the laminate changes. Our layer assignment notes describe how the stack is planned around those constraints.
Impedance Tolerance and What Drives It
An impedance specification is meaningless without a tolerance. A typical requirement is plus or minus ten percent, and tighter tolerances of five percent are achieved by controlling the dielectric thickness more closely, which costs more. The tolerance is driven by three things: the variation in dielectric thickness across a panel, the variation in dielectric constant between panels of the same material, and the variation in etched trace width.
Echo effects matter here. A periodic variation in trace width along a route produces a periodic change in impedance, which reflects energy at the spatial frequency of the variation. A fabricator who can hold the width and the thickness will hold the impedance, which is why the acceptance test is a coupon measurement rather than a calculation.
Verification on the Panel
Impedance is verified with coupons built into the panel border. The coupon contains structures that match the geometry of the traces on the board, and it is measured with a time domain reflectometer or a network analyser. Because the coupon is built on the same panel with the same process, it measures what was produced rather than what was designed.
The measurement is usually made on every panel for a production run, and the results are recorded. Where the reading is outside tolerance, the fabricator can adjust the process for the rest of the run, which is only possible because the coupon is measured early rather than at the end. Our design release checklist places that measurement in the sequence.
Design Practices That Preserve the Number
What breaks impedance is the layout rather than the calculation. A trace that widens to pass around a component, that crosses a plane split or that runs over a region where the reference plane has been removed for a connector has a local impedance that differs from the design value, and that discontinuity reflects energy.
The defensive practices are simple. Keep a continuous reference plane under every controlled impedance trace. Avoid plane splits and, where one is unavoidable, bridge it with stitching capacitors rather than allowing a gap. Keep the number of vias in the trace to a minimum and, where a via is required, provide ground vias close to it so the return path stays continuous. Keep the wave soldering or connector keep-out areas free of controlled impedance routing, and verify the finished geometries on the coupon rather than assuming the layout was reproduced exactly. Our component tolerance and reliability notes describe how those discontinuities are assessed.
Layer Count and Reference Plane Planning
Controlled impedance needs a reference plane, and the reference plane needs a layer of its own. That is the usually unstated reason why a board with high speed interfaces needs at least four layers: the outer layers carry components and routing, and the inner layers provide the plane and the power distribution. A two layer board can support controlled impedance in principle, by using the opposite side as a reference, but any routing on that side breaks the plane beneath the trace and destroys the impedance locally.
The stack should therefore be planned before the routing begins, and the plan should allocate each signal layer a reference plane that is not shared with anything that would compromise it. Where a layer must reference a power plane rather than a ground plane, the return current flows in the power plane, and the impedance calculation changes because the power plane is not at zero potential. It works, but it has to be calculated rather than assumed.
FAQ
At what signal speed does controlled impedance become necessary? The criterion is the rise time rather than the clock frequency. Once the rise time is short compared with the round trip delay along the trace, reflections arrive during the bit and the link requires a controlled impedance.
Can the same stack support several impedances? Yes, by varying the trace width and the differential spacing on the same layer. Fabricators routinely build coupons for three or four different impedances on one panel.
Does solder mask affect impedance? Slightly, because it sits above the trace and forms part of the dielectric. Good calculators and fabricators account for it, and ignoring it adds a small error that matters only at tight tolerances.
