Fabrication Data Pitfalls That Delay a Prototype
Fabrication data problems are rarely caused by a design being wrong. They are caused by the data being ambiguous, and the cost appears as a query from the fabricator, a delay in the schedule or a panel that has to be reworked. Most of these problems are visible before the files are sent, and each of them has a straightforward fix.
Ambiguous Layer Definitions
The most common cause of delay is a layer stack-up that has not been explained. A single-sided design placed on the top layer, or a four-layer design ordered as top, inner one, inner two and bottom, will be interpreted by the fabricator according to its own convention unless the intended order is stated. Where the data uses different names for the same layer, or arranges them in an order that does not match the physical stack, the interpretation has to be confirmed by discussion rather than by reading the file.
The remedy is a layer table in the fabrication notes: which data layer corresponds to which physical layer, which direction each is viewed from, and which layer defines the outline. That table removes an entire class of question.
Fill Blocks and Fine Lines in the Artwork
Large areas of copper are usually represented as filled regions rather than as individual lines, and the way those regions are defined matters. A filled area that is constructed from very fine parallel lines produces a large volume of drawing data, which slows the data preparation step and can lead to lost or incomplete photoplotting output. On a board with several such areas the data volume becomes a practical problem rather than a theoretical one.
Regions should therefore be drawn as solid fills or as hatched patterns with a sensible line width, rather than as a dense array of hairlines. The same applies to any copper fill that is used for balance rather than for conduction. Our copper balance notes describe how fill areas are used and what they should look like in the data.
Pads That Are Too Short for Test Access
A pad that is adequate for the component may still be inadequate for the test probe. On a dense assembly, the spacing between adjacent pads is small and the pads themselves are narrow, and the test fixture needs to reach them from above or below with the probes staggered. A pad that is too short does not prevent the component from being soldered, but it can make the probe slide off, which shows up as a false failure or as damage to the fixture.
Where a design will be tested with a fixture, the pad geometry has to accommodate the probe as well as the component. That requirement is easier to satisfy at the layout stage than to work around in the test programme. Our flying probe notes describe the alternative where fixture access is impractical.
<img src="https://www.gopcba.com/wp-content/uploads/2025/05/员工风采.jpg" alt="Routed board outline with copper clearance on a PCB panel” />
Copper Too Close to the Outline
A large copper area that extends to the board edge creates a problem in the routing step. The milling tool that cuts the outline will pass through the copper, and the burr that forms can lift the copper and detach the solder mask over it. A clearance of at least a couple of tenths of a millimetre between the copper and the outline avoids this, and the requirement applies to planes, fills and wide traces alike.
The same reasoning applies to internal cut-outs. A slot or cavity that comes too close to a copper feature will damage it during milling, and the damage is not always visible until the board is assembled.
Grid Spacing and Membrane Residue
A large hatched copper area with an opening smaller than about three tenths of a millimetre creates a manufacturing risk. During imaging and development, resist residue can be trapped in the narrow openings and remain on the board, and the residue interferes with the subsequent etching or plating step, producing broken conductors. Hatched patterns therefore need openings that the process can clear, and the design should specify the opening rather than leaving it to the fabricator’s default.
Non-Uniform Patterns and Plating
Plating quality depends on the distribution of the pattern. A board with dense copper in one region and almost none in another will plate unevenly, because the current density varies across the panel, and the uneven thickness affects both the etching result and the impedance. Adding balance features to the sparse regions, or arranging the panel so that the density is more uniform, is the usual remedy.
The same principle applies within a single board: a layer that is almost entirely copper opposite a layer that is almost empty creates a mechanical and a plating problem at the same time.
Outline Definitions and Odd-Shaped Holes
An outline drawn on several layers with different geometry is a design fault that has to be resolved before fabrication. Where the keep-out layer, the mechanical layer and the silkscreen outline do not coincide, the fabricator has to ask which one is authoritative, and the answer may not be the one the designer intended.
Slots and odd-shaped holes have their own limits. An elongated hole should have an aspect ratio of at least two to one and a width above about a millimetre, because a narrower slot is difficult to drill without breaking the tool, which raises the cost and reduces the yield. Where a narrower slot is essential, routing rather than drilling is the appropriate method. Our board outline notes and the fabrication notes guidance cover how to specify both.
Drill Tables and Plated Openings
A drill table that lists tool sizes without stating which of them are plated leaves the fabricator to infer the intent, and the inference is not always the intended one. Non-plated openings are drilled at a larger finished size than plated ones, and a tool that appears once in the table but serves both purposes cannot be interpreted from the drawing alone. The fix is a column that states, for each tool, the finished size, the plating condition and the quantity.
Via-in-pad and filled via constructions need the same treatment. Where a via is to be filled and capped, the fabrication notes should say so, together with the requirement that the surface be planar enough for the component to sit flat. Without that statement, the data is consistent but the process is undefined, and the resulting voids appear later as solder defects under the part rather than as a data query. Our fabrication notes guidance lists the items to state explicitly.
FAQ
Why does a filled copper area cause a data problem? Because the way the fill is described in the data determines how much information the fabricator has to process. A region built from thousands of hairline segments is far heavier than the same region drawn as a solid polygon, and the heavier version can exceed the limits of the photoplotting step. Drawing fills as solid regions or as hatched areas with a realistic line width avoids the issue.
How close can copper be to the board edge? At least a couple of tenths of a millimetre, and more where the outline is routed rather than punched. The clearance protects the copper from the cutting tool and prevents the mask from being lifted by the burr that the cut produces. It should be checked as part of the design rule set rather than by eye.
What does gopcb ask for when the data is ambiguous? We ask for the layer table, the outline definition and the intended stack-up, and we state our interpretation in the fabrication review so that the customer can correct it before the panel is released. Almost every data-related delay we see is traceable to one of those three items being absent or inconsistent.
