Blind and Buried Via Design Rules: An HDI Stack-Up Guide

Blind and buried vias are the reason a dense board can be routed at all. They let a signal travel between two inner layers without drilling through the whole panel, freeing the surface for components and shortening the return path for high-speed nets. They also multiply the number of fabrication steps, so the design rules that surround them are stricter than most designers expect.

What Blind and Buried Vias Allow

A buried via connects inner layers and is completely enclosed by laminate after lamination, which means it can pass under surface pads, connectors and shields without blocking them. A blind via starts on an outer layer and ends on an inner one, so it opens only one side of the board. Together they let a designer separate the routing channels of different layer pairs.

The payoff is density and electrical performance. Short vias have less stub, lower inductance and less capacitance to the surrounding planes, so they behave better at multi-gigahertz frequencies. The cost is process complexity: every distinct via span must be drilled, plated and filled at a different point in the lamination sequence, and each extra step adds yield risk and lead time.

The Fabrication Sequence Behind Every Buried via

Buried vias force the panel to be built in stages. The inner core pairs are drilled and plated first, then laminated together with prepreg, then drilled again for the next via span, and so on. Each lamination cycle subjects the material to heat and pressure, and each drilling operation has to register to features that are already buried inside the panel and therefore invisible.

That registration requirement is what drives the design rules. Features buried inside the stack cannot be measured directly, so they must be targeted through the material or located by reference to tooling holes. The HDI blind and buried via process guide explains how many sequential laminations a given build implies and why that number dominates the quotation.

Aspect Ratio Limits and Drilling Capability

Depth-to-diameter ratio, usually called aspect ratio, sets the practical limit for any plated hole. A blind via drilled 0.1 mm in diameter through a 0.1 mm dielectric has an aspect ratio of 1:1 and plates easily; a hole 0.3 mm deep at the same diameter is 3:1 and is much harder to fill with uniform copper. Plating solution must reach the bottom of the barrel and exchange with fresh chemistry.

Blind vias are drilled by laser or by controlled-depth mechanical drilling, and each method has its own minimum diameter and depth tolerance. Laser drilling gives small, shallow holes with good repeatability; mechanical drilling reaches deeper but needs more clearance. The aspect ratio guide gives the working ranges that fabricators accept without special negotiation.

Pad, Annular Ring and Registration Tolerances

Every additional lamination and drilling cycle adds registration error, and the annular ring has to absorb all of it. A buried via sitting on a plane needs a pad large enough that a misregistration of 0.05 mm in either direction still leaves copper all round the hole. Shrinking the pad to gain routing space removes exactly the margin that the process needs.

The same logic applies to the capture pads on outer layers. Blind vias open to the surface, so their pads are also landing targets for components, and the combined tolerance stack includes drilling, lamination, imaging and the component placement accuracy. The tooling hole and registration guide shows how a panel is aligned between these steps and where the cumulative error accumulates.

Stack-Up Planning Before You Place a Single Via

Via spans have to be defined before routing, because they determine the lamination sequence and therefore the layer order. Deciding later that a net needs a buried via between layers three and four may be impossible if those layers end up separated by a core that cannot be drilled in a later stage. The stack-up and the via schedule are one decision, not two.

A practical approach is to list the layer pairs that genuinely need short vias, build the stack-up around those spans, and let everything else use through vias. Most boards need surprisingly few blind and buried spans; using them everywhere multiplies cost for no measurable benefit. Layer assignment rules from the multilayer design rules are a useful cross-check at this stage.

Via Fill, Plating and Reliability

Buried vias are filled with resin or plated shut before the next lamination so that the copper above and below them is supported and the dielectric does not collapse into the hole. Incomplete fill leaves voids, and voids trapped inside the stack can expand during reflow, cracking the barrel or delaminating the surrounding laminate. Via fill is not cosmetic; it is a reliability requirement.

Conductive fill is used where the via sits under a pad and must also carry current or conduct heat, and it is often combined with plating and planarisation so the pad surface stays flat enough for solder paste. Filling quality is verified by cross-section on the first articles, which is why prototype builds of HDI boards normally include a coupon.

Cost, Lead Time and Layer Pair Choices

Cost in an HDI build is driven almost entirely by the number of sequential lamination cycles. One extra cycle can add several working days and a significant fraction of the board price, because the panel passes through drilling, plating, imaging and lamination again. Reducing the number of distinct via spans is the single most effective cost lever available to a designer.

The second lever is via count within a span. A span that is used for two hundred holes costs far more than one used for ten, since the process steps are the same either way. Consolidating vias onto shared spans, and keeping diameters at or above the fabricator’s standard minimum, keeps a dense design inside a normal price band.

Design Rule Checks and Documentation

Standard design rule checking rarely understands via spans. A check that confirms annular ring on a through via may say nothing about whether a blind via has enough captured pad on the layer it lands on, or whether two vias in different spans overlap in the vertical direction. Custom checks, or a careful manual review of each span, are necessary.

Documentation should list every via span explicitly, with diameter, depth, fill requirement and the layers it connects. A drawing that simply says blind and buried vias required leaves the fabricator to infer the intention from the artwork, and inference is how expensive misunderstandings begin. The fabrication notes checklist covers the items worth stating up front.

Common Mistakes That Force a Re-spin

The most frequent mistake is a via span that cannot be built, either because the dielectric is too thin to drill reliably or because the aspect ratio exceeds what the process can plate. The second is a blind via that lands on a plane with no clearance, shorting the net the moment the hole is drilled through the copper beneath it.

The third is documentation drift, where the artwork is updated but the via schedule is not, so the fabricator builds an earlier intent. Every revision should be checked against the drawing, and any change to layer order should trigger a fresh review of every span. gopcb asks for the via schedule on the first enquiry precisely to catch these issues before drilling begins.

FAQ

How many blind and buried via spans should a design use? As few as possible. Each span adds a lamination cycle and a drilling step, so consolidating to two or three spans usually gives most of the routing benefit at a fraction of the cost.

Can buried vias be repaired if they fail? No. A buried via is enclosed in laminate and cannot be accessed after assembly. Reliability has to come from correct fill, adequate plating and verified process control on the first articles.

Do blind vias always need filling? Vias that open onto a pad used for soldering should be filled and plated over to prevent paste loss. Vias that are tented and not soldered can remain unfilled, provided the fabrication note says so.