Verifying PCB Impedance with TDR Measurement Techniques
Controlled impedance is a promise made in the stackup drawing and verified somewhere far downstream, usually with a time domain reflectometer and a coupon that travels with the panel. The measurement looks simple on a screen, yet the number it produces depends on the coupon, the probe, the rise time, and the way the trace is interpreted. This guide explains how to make that verification meaningful instead of merely reassuring.
Why Impedance Verification Matters
A high-speed link is designed around an expected characteristic impedance, commonly 50 ohms single-ended or 100 ohms differential. If the fabricated trace drifts away from that value, reflections rise, eye diagrams close, and margin that the simulation assumed simply is not there. Because impedance depends on geometry the fabricator controls, verification is the only way to know the promise was kept.
The tolerance is usually expressed as a percentage, plus or minus ten percent being common and tighter values reserved for demanding interfaces. Verification also protects the fabricator, because it turns an argument about performance into a documented measurement with a defined method. Agreeing on that method before production prevents disputes later.
How TDR Measurement Works in Practice
A time domain reflectometer launches a fast step or pulse into the trace and records the reflection that returns. Impedance changes along the path produce reflections whose amplitude and timing reveal where the change occurred. Converting the time axis into distance using the trace’s propagation velocity yields an impedance profile along the line.
The instrument itself is usually a sampling oscilloscope with a step generator, or a dedicated TDR module. Its rise time limits the spatial resolution, and its calibration removes the effects of cables and connectors. Skilled operators treat the launch as part of the measurement rather than an unavoidable nuisance, because a poor launch creates a large reflection that can mask the trace they actually want to characterise.
Designing the Impedance Test Coupon
A test coupon must reproduce the production geometry exactly. That means the same layer, the same trace width and spacing, the same copper thickness, and the same soldermask treatment as the boards it represents. A coupon drawn with generous spacing on an outer layer tells you nothing about the tightly coupled inner-layer pairs on the product.
Length matters as well. The trace should be long enough that launch and end effects occupy a small fraction of the measured window, yet short enough to fit sensibly on the panel. Place coupons in more than one position across the panel, since plating thickness and etch variation mean the middle and the edges rarely measure identically.
Launch, Probe and Fixture Effects
The point where the probe contacts the coupon is a discontinuity, and it always shows up as a spike on the profile. Good coupon design minimises it with a short, wide launch pad on a ground-referenced layer, often with ground vias close to the signal via. The goal is a transition that the operator can identify and exclude from the impedance window.
Probe type and grounding also matter. A hand-held probe with a long ground lead adds inductance that distorts the leading edge, while a properly grounded high-bandwidth probe introduces far less. Fixtures bring their own impedance, so their effect must be characterised with a reference or calibration structure before production traces are measured.
Rise Time, Resolution and Bandwidth
Rise time determines how small a feature the TDR can resolve. A fast edge sees short discontinuities and narrow traces; a slow edge averages them out and reports a smoother, more flattering profile. This is why the specification should state the rise time, because two labs using different instruments can report different values for the same coupon.
Bandwidth and cable quality set the practical limit on the edge. Long, lossy cables slow the transition and reduce resolution, which is one reason measurements are normally taken close to the board. If a customer requires verification at a particular rise time, that requirement belongs in the purchase specification, along with the instrument class needed to meet it.
Reading the Trace and Setting Windows
A TDR trace begins with the launch spike, then settles to a plateau that represents the trace impedance, and ends with a reflection from the termination or the open end. The useful measurement is the average over a defined region in the middle, where launch and termination effects are excluded. Reporting the peak or the value at a single point invites cherry-picking.
Windows should be defined in the specification, together with the statistic, normally the mean over the region and sometimes the maximum deviation. Smoothed averaging over a defined length mimics what the signal will experience. Document these choices so that a change in operator or instrument does not silently change the acceptance criterion.
Differential Pair Measurements
Differential pairs are measured differently. The instrument may drive both lines and measure differential impedance, or drive one line at a time to extract the odd-mode and even-mode values. Intra-pair skew, the difference in propagation delay between the two traces, also matters and is often measured alongside impedance on the same coupon.
Coupon design for differential structures needs symmetrical routing, matched lengths, and adequate ground referencing. Asymmetry caused by a nearby via or a reference plane split will show as a bump in the profile that no amount of process adjustment can remove, because the geometry, not the process, produced it.
Correlating TDR Results with Cross-Sections
When a coupon measures out of tolerance, the next step is a microsection of an adjacent coupon or a scrap area. The section reveals the actual trace width, dielectric thickness, and copper thickness, which often explains the result immediately. Correlation between the electrical measurement and the physical structure is the fastest route to a corrective action.
Keep both data sets together in the lot record. If TDR says high and the section shows a thin dielectric that matches the design, the stackup may need adjusting rather than the process. If the section shows a width narrower than the artwork, the etch process is the place to look. Neither measurement alone tells the whole story.
Sampling, Records and Disposition
Sampling frequency should reflect the criticality of the product. Prototypes usually warrant full verification of every coupon on the panel, while a mature product may move to a per-lot sample with periodic full checks. Define who measures, when, and what happens when a result falls outside the window before production starts.
Disposition rules should cover the marginal case as carefully as the obvious failure. A coupon a few percent out may be acceptable if the link budget allows, and unacceptable if it does not. Record the decision with the measurement data so that the reasoning can be reviewed later, and feed the results back into the design rules for the next revision.
FAQ
How often should impedance be measured? Measure every coupon during prototyping and first production, then move to a documented sampling plan once the process proves stable. Any change in laminate, stackup, plating, or etch parameters should trigger a full verification rather than a sample, because those are the inputs that move impedance.
Why does my TDR reading differ from the fabricator’s? Difference usually comes from probe type, ground lead length, rise time, and the window over which the value is averaged. Agree on the instrument class, the coupon location, and the reporting region, then compare using the same coupon to separate genuine process variation from measurement technique.
Can impedance be checked without a coupon? With difficulty. Measuring a product trace requires probing on the board itself, where components, mask, and geometry complicate the launch and the result. Coupons exist to provide a clean, repeatable structure, and they remain the standard method for acceptance testing.
