High Speed ADC Clock Design: Jitter and Sampling Stability

In a high speed data conversion system the clock is not a support function, it is part of the measurement. An adc samples the input at the instant the clock edge arrives, so any uncertainty in that instant becomes uncertainty in the value that is converted, and no amount of filtering afterwards can remove it.

Why Clock Stability Limits Performance

The converter captures an instantaneous value of a changing signal. If the sampling instant moves, the captured value changes even though the input has not, and the resulting error appears as noise in the digital output rather than as an obvious distortion.

That is why the clock specification is treated as an analogue parameter. Jitter and duty cycle variation translate directly into a reduction in the signal to noise ratio and in the effective number of bits, which is the performance the customer measures.

How Jitter Becomes Noise

The magnitude of the error depends on how fast the input is changing. A signal with a high slew rate produces a larger voltage change for the same timing error, so the noise contribution of a given jitter grows with input frequency and amplitude.

Clock jitter is not the only source. The aperture uncertainty inside the converter adds to it, and the two combine as a root sum of squares. Once the external clock is quieter than the converter’s own aperture jitter, further improvement in the clock brings nothing.

Aperture Jitter and Effective Bits

Aperture jitter describes the uncertainty in the sampling instant, and it is quoted in picoseconds or femtoseconds. Where it was once measured in picoseconds, the best converters now achieve tens of femtoseconds, and a clock that adds more than that simply gives the performance away.

The practical target follows from the resolution and the input frequency. Higher resolution and higher input frequency both tighten the requirement, which is why a 16 bit converter at high sampling rates demands a clock source that would have been unnecessary a generation ago.

Duty Cycle and Sampling Instant

Many converters sample on one edge and use the other for internal timing, so the duty cycle matters as well as the edge rate. A clock that is not close to fifty percent can shift the internal timing and reduce the available settling time.

Duty cycle stabilisation circuits inside the converter help, but they work best with a clean input. A clock that is asymmetric and jittery defeats them, and the effect appears as a loss of dynamic range that is easy to misattribute to the analogue front end.

Clock Sources: Oscillator, PLL and DLL

A low jitter oscillator placed close to the converter is the simplest solution and usually the best for phase noise, because no multiplication is involved and the signal travels the shortest possible distance.

Where the clock has to be derived or multiplied, a phase locked loop introduces its own noise, and reference spurs appear at predictable offsets. A delay locked loop avoids the accumulating phase error of a voltage controlled oscillator and is preferred where the requirement is to align or deskew a distributed clock rather than to synthesise a new frequency.

Distributing the Clock Across the Board

On a converter board the clock may have to reach several devices, and the distribution network becomes part of the specification. A fanout buffer with matched outputs is preferable to daisy chaining, because each additional load changes the edge and adds a reflection.

Length matching keeps the sampling instants aligned across multiple converters. Where the physical distances differ, the length matching technique used for any synchronous bus applies, with the same requirement that the added length does not introduce avoidable coupling.

Grounding and Return Path

The ground plane under a clock net is part of the circuit, because a clock is a signal with a return, and the return path has to be as well controlled as the trace. A continuous reference immediately beneath the clock trace keeps the loop small and prevents the switching energy from spreading into the analogue section.

The ground under the converter and its clock should be treated as one quiet region, as described in general mixed-signal practice. Splitting it into unrelated areas forces the return current to detour, which is worse than a single well planned reference.

Supply Noise and Decoupling

The clock buffer and the converter share supplies with other circuits, and noise on those rails modulates the switching threshold of the clock input, which converts supply noise directly into jitter.

Separate regulation, local decoupling and a quiet power plane region all reduce the coupling. The decoupling belongs at the device rather than at the edge of the block, and the connection from the capacitor to the supply pins should be as short as the layout permits. The same discipline applies to the wider supply distribution described in power trace planning.

Layout Rules for Clock Traces

Keep the clock trace short, direct and away from switching nodes. Do not route it parallel to digital data or across a plane split, and avoid stubs and vias that create reflections, since a reflection degrades the edge and therefore the accuracy of the threshold crossing.

Where the clock must travel, a controlled impedance trace with a defined reference and minimal discontinuities preserves the edge shape. Terminating correctly matters more than matching the nominal impedance exactly, because an unmatched line produces an edge that both the converter and its sampling instant will notice.

Verification

Verification looks at the clock rather than the converter first. Measure the phase noise or the jitter of the source, then measure it again at the converter pin, because the distribution network can add more than the source itself contributes.

Confirm the result by measuring the converter’s signal to noise ratio against its datasheet limit. If the measured performance falls short while the analogue path is clean, the clock is the first place to look, and the measurement at the pin usually identifies whether the source or the routing is responsible.

Clock Interface and Signal Level

The electrical interface between the source and the converter should be chosen deliberately. Differential clocks with a defined common mode are more tolerant of noise and of ground shift than single-ended types, which is why they are used wherever the converter supports them.

Signal amplitude matters as well. A large swing produces a faster edge but couples more energy into neighbouring structures, while a small swing is quieter but more sensitive to noise on the reference. The interface standard usually settles the compromise.

Common Design Mistakes

The most frequent error is routing the clock as though it were an ordinary digital signal: long, unbuffered, sharing a return with switching currents and crossing a plane boundary on the way to the converter.

The second is treating decoupling as a formality. A clock buffer that draws its switching current through a shared trace sees the supply move with every edge, and that movement appears as jitter in the output rather than as an obvious supply problem.

FAQ

How much jitter is acceptable? It depends on the resolution and the input frequency. The requirement is that the clock contribution stays well below the aperture jitter of the converter itself, or it becomes the limiting factor.

Is a PLL always worse than a crystal oscillator? Not always, but a PLL adds its own noise and spurs. Where a direct oscillator can be placed close to the converter, it is usually the quieter solution.

Can the clock improve a noisy analogue front end? No. A clean clock preserves the performance that the analogue path already has, and it cannot recover accuracy that has been lost before the sampling instant.