Stack-up Planning: Layers, Dielectric Thickness and Cost

The stack-up is the decision that determines the impedance, the routing capacity, the cost and the fabrication yield of a board. It is usually made early, often by default, and revisited only when something has gone wrong.

What the Stack-up Determines

The number of layers sets the routing capacity and the number of reference planes available. Each signal layer needs an adjacent reference, and the count of signal layers therefore depends on the count of planes.

The dielectric thickness between a signal layer and its reference sets the trace width required for a given impedance. A thin dielectric gives a narrow trace for the same impedance, which allows denser routing.

The build-up also determines the process steps required. A sequential lamination has more steps, more opportunities for misregistration and a higher price. Our layer assignment notes describe the pairing of signal and plane layers.

Starting From the Requirements

The inputs are the number of signal nets that must be routed, the impedance targets, the frequencies involved and the mechanical thickness available.

A useful first estimate is that a signal layer can route roughly one net per millimetre of board width for a fine pitch design, and the number of layers follows from the total net count and the number of signal layers the stack can support.

Where the mechanical thickness is fixed by an enclosure or a connector, the sum of the dielectric and copper thicknesses must fit, which constrains the number of layers that can be used. Our layer count notes describe how the count is estimated.

Symmetric Build-ups

An asymmetric stack, with more copper or more dielectric on one side, warps during lamination and during reflow. The resin shrinks as it cures, and the amount of shrinkage depends on the amount of resin and copper on each side.

A symmetric build-up balances the copper weight and the dielectric thickness about the centre, which keeps the board flat. The symmetry requirement constrains the layer assignment, since a signal layer added on one side must be matched on the other.

Where symmetry cannot be achieved, it is often cheaper to make the board thicker than to work with a warped board, and the fabrication house can advise on how far the asymmetry can be pushed. Our laminate properties notes describe how the material behaves.

Choosing the Dielectric Thickness

The dielectric thickness between a signal layer and its reference is chosen to give a practical trace width for the target impedance. Very thin dielectrics give very narrow traces, which are harder to etch and whose impedance is more sensitive to the etch tolerance.

Very thick dielectrics give wide traces, which consume routing space and make the impedance more sensitive to the soldermask and to the copper thickness.

The practical range for a controlled impedance microstrip on a common laminate is on the order of one hundred to two hundred micrometres, and the exact value depends on the laminate’s dielectric constant. Our high speed design rules notes describe the calculation.

Cost Considerations

The cost of a board rises with the layer count more quickly than linearly, because each additional layer adds lamination, drilling and imaging steps and reduces the yield.

An expensive material is only worth using on the layers that need it. Where a design needs a low loss laminate for one high speed link and a standard material for the rest, a hybrid stack places the expensive material where it matters.

A hybrid stack adds process complexity because the two materials behave differently during lamination, and the fabrication house must be consulted before the design is committed. Our cost reduction notes describe how the trade is evaluated.

Documenting the Stack-up

The stack-up should be drawn rather than described, with the layer order, the copper weight and the dielectric thickness of each layer, and the impedance target for each controlled layer.

A description in prose is ambiguous, because the terms used by different suppliers differ. A drawing removes the ambiguity and gives the fabricator something to price against.

The finished thickness of the board should also be specified, with a tolerance, since the sum of the layers does not always equal the nominal. Our fabrication notes describe what the drawing should contain.

Revisiting the Stack-up

A stack-up is worth reviewing when the design changes in a way that affects it: a new net count, a new impedance requirement, a change of connector or enclosure, or a cost reduction exercise.

The review should be done before the design is released, and it should include the fabricator. A stack that the fabricator cannot build reliably at the required yield is not a stack-up, it is a wish.

Where a design is expected to be reused for several products, the stack-up should be designed for reuse rather than for one product. A well chosen stack can serve a family of boards and reduce the work of the next design.

Process Control and Verification

On a design of this kind, impedance is the item that decides how the rest of the board is arranged. Where the requirement is not written down, the shop supplies its own default, and the default is chosen for the process rather than for the design. The measurements that matter are the repeatable ones: conductor width and spacing, annular ring, finished hole size, plating thickness and surface finish are all verifiable on a coupon that travels with the panel.

Running a first article through the same checks as the production panel confirms that the two agree, and that comparison is the cheapest form of process control available at prototype stage. Keeping a sample from the panel turns a dispute into a measurement, because the same coupon can be re-examined by both parties without rebuilding the batch.

Process Control and Verification

On a design of this kind, impedance is the item that decides how the rest of the board is arranged. Where the requirement is not written down, the shop supplies its own default, and the default is chosen for the process rather than for the design. The measurements that matter are the repeatable ones: conductor width and spacing, annular ring, finished hole size, plating thickness and surface finish are all verifiable on a coupon that travels with the panel.

Running a first article through the same checks as the production panel confirms that the two agree, and that comparison is the cheapest form of process control available at prototype stage.

Process Control and Verification

On a design of this kind, impedance is the item that decides how the rest of the board is arranged. Where the requirement is not written down, the shop supplies its own default, and the default is chosen for the process rather than for the design. The measurements that matter are the repeatable ones: conductor width and spacing, annular ring, finished hole size, plating thickness and surface finish are all verifiable on a coupon that travels with the panel.

FAQ

How many layers do I need? The count follows from the net count, the routing density and the requirement for a reference plane adjacent to every signal layer, which can be estimated before layout begins.

Can a stack-up be changed after layout? It can, and it changes every impedance and every trace width, which means redoing the controlled impedance routing. The decision should be made early.

What does gopcb provide for stack-up planning? We provide symmetric build-ups for the required impedance and routing density, dielectric and copper selections with the tolerance implications, hybrid stacks where a low loss material is justified, and a drawing that the fabricator prices against.