Blind Via Filling Guide

A blind via connects an outer layer to an inner layer and stops without passing through the board. When another via has to be placed directly above it, or when the via lies in a pad that must be printed flat, the hole has to be filled rather than left open. Blind via filling is the process that achieves this, and its quality is measured by the absence of voids, the flatness of the surface and the adhesion between the fill and the barrel.

Why a Via Is Filled

The first reason is stacking. A via on via structure in an HDI board requires the lower via to be filled and capped so that the next layer has a flat copper surface to drill into. An open via would trap plating solution, leave a dimple and create a weak point.

The second reason is printing. A via that is open in a pad wicks paste away from the joint during reflow, which starves the joint and leaves a void in the thermal interface. Filling and capping removes the reservoir and gives the pad a printable surface.

The third reason is reliability. A filled via supports its own barrel, which reduces the strain under thermal cycling and removes the cavity that would otherwise collect process chemistry.

Filling Materials

A non conductive fill is an epoxy paste loaded with a mineral or a silica filler. It is applied, cured and then planarized, and a copper cap is plated over it if the via has to carry a stacked connection.

A conductive fill uses a paste loaded with copper or silver particles, and it is used where the via carries current or heat and where the plating of a cap is not practical. The thermal expansion and the conductivity both differ from the non conductive type.

The choice depends on the function. A via that only needs to be flat is filled with the cheaper non conductive material, while a via that forms a thermal path or a stacked electrical connection needs a conductive fill or a copper filled barrel.

The Filling Process

The paste is applied with a squeegee or a dispenser over the panel, and the holes are filled from one side. The panel is then cured, and the excess material on the surface is removed by planarization.

Voids are the main defect. They come from air trapped as the paste is pushed into the hole, from the solvent that escapes during cure and from a hole that has a shape that the paste cannot fill from the application side.

The cure has to be controlled. A fast cure traps solvent inside the fill and produces a void that appears later, while an incomplete cure leaves the material soft and it is removed unevenly during planarization.

Planarization and Copper Capping

Planarization removes the fill and the plating that sit above the surface, and it is done by mechanical grinding, by chemical mechanical polishing or by a combination of the two. The result should be a surface that is flat enough for the next layer to be laminated over it.

Copper capping follows the planarization where a stacked via is required. The cap is plated over the filled and planarized via, and the plating has to bond to the copper of the pad as well as to the fill.

A dimple is the characteristic defect of this stage. A slight recess at the centre of the via is acceptable in some specifications and not in others, and the limit should be stated as a dimension rather than as a visual impression.

Void and Adhesion Requirements

The void content is usually specified as a maximum percentage of the via volume, and it is measured by X ray or by a section. The measurement is difficult because a void inside a filled via is small, and the sample has to be prepared carefully to avoid pulling the fill out.

Adhesion between the fill and the barrel is the second requirement. A fill that has separated from the wall leaves a gap that plating solution can enter during the next process step, and the trapped chemistry is a long term reliability risk.

The specification should also cover the fill material itself, including its coefficient of thermal expansion. A fill that expands more than the surrounding copper will push the cap off during thermal cycling, and the failure appears at a temperature rather than at a time.

Process Control

The paste has to be used within its pot life and stored under the specified conditions. A paste that has thickened will not fill the hole completely, and the result is a partially filled via that passes a visual check.

The squeegee or the dispenser parameters set the volume that is applied. Too little and the holes are not filled, too much and the excess is wasted and has to be removed in a step that risks damage to the surface.

The hole geometry matters as much as the process. A hole with a large aspect ratio or with a rough wall is difficult to fill, and the fill quality should be verified on a coupon that represents the worst case hole in the design.

Inspection and Verification

A section is the most informative inspection, because it shows the fill, the voids and the adhesion in a single image. The sample should be taken from a position on the panel that represents the production distribution rather than from the centre only.

X ray shows the voids in a filled via as well as the barrel, and it can be used on a sample basis to check the process without destroying the panel. The limit of the method is the resolution at small via diameters.

The electrical test should include a check of the resistance through a stacked via structure, because a fill that has separated can still pass a continuity test when the cap is intact. The resistance test is more sensitive than a continuity test.

Where It Fits in the Design

Blind via filling is a requirement of HDI designs that stack vias, and it should be specified at the stackup stage rather than added after a plating defect appears. The fabricator should state which vias will be filled and how they will be capped.

The rule set should describe which vias are filled, which are capped and which are left open, because the three have different electrical and thermal behaviour. A design that leaves the choice to the fabricator will receive a board that meets the drawing and not the intent.

The cost is linked to the number of vias that are filled and to the number of fill and planarization cycles. A design that stacks vias through several layers pays for the process at each layer, which is why the stackup should be arranged to minimise the number of stacked connections.

Practical Rules

Specify the fill material, the void limit, the dimple limit and the cap requirement on the drawing. Verify the fill on a coupon that represents the worst case hole, and check the resistance through a stacked structure.

Record the fill and inspection data with the build records and the dimensional stability data, and review the via filling plating and the HDI via process when a stacked structure is planned.

FAQ

Why fill a blind via rather than leave it open? An open via wicks solder out of a pad, traps plating solution and cannot support a stacked via above it. A filled and capped via gives a flat copper surface.

What is the main defect of via filling? Voids, from trapped air or from solvent that cannot escape during cure. A void inside a filled via is small and is usually found by a section or by X ray.

Does the fill have to be conductive? Only if the via carries current or heat or forms a stacked connection. Otherwise a non conductive epoxy fill with a plated cap is sufficient.