Decoupling Capacitor Placement and Via Design
A decoupling capacitor does one job: it supplies charge to a device faster than the power supply can respond. Whether it succeeds depends far more on the loop between the capacitor and the device than on the capacitance value printed on the part.
The loop is made of copper, and it has inductance. Placement and via arrangement decide how much inductance the loop has, and the inductance decides which frequencies the capacitor can actually address.
What the Capacitor Has to Do
When a device switches, it draws a current step that the supply cannot deliver immediately. The capacitor supplies that step, and the voltage disturbance at the device depends on the impedance of the path between them.
The path includes the capacitor’s own equivalent series inductance, the pads, the traces or planes and the vias. At high frequency the inductance dominates, and a larger capacitor with the same loop behaves no better than a small one.
Loop Inductance and Placement
The most effective measure is to place the capacitor as close to the device pin as the layout allows, which reduces the area of the loop. A capacitor three millimetres away has a loop that is several times longer than one placed directly beside the pin.
The loop area, not the distance, is what matters, so a capacitor placed close but with a long return path may be worse than one placed further away with a short one. The rule is to keep the supply and the return adjacent.
Via Placement and Via Count
Each via adds inductance, and a capacitor connected by one via per terminal has roughly the inductance of two vias in the path. Using two vias per terminal, placed on opposite sides of the pad, reduces the inductance and also lowers the resistance.
The vias should be as close to the pad as the fabrication rules permit, with the shortest possible connection, since a stub of trace between the pad and the via contributes inductance without contributing anything else.
Traces Against Planes
A capacitor connected to the device by a trace has the inductance of that trace in the loop. Connecting it directly between the power and ground planes removes the trace and leaves the planes as the path, which is the reason a plane pair is used on any board with a fast device.
Where the capacitor must connect to a plane, the connection should be by via rather than by a long trace along the plane surface. This is a small layout detail with a disproportionate effect, similar in character to the issues covered in mixed signal design.
Capacitance Value and Self Resonance
Every capacitor has a self resonant frequency above which it behaves inductively, and above that point it no longer decouples. A large capacitor mounted at a device pin can therefore be less effective than a small one at the frequencies that matter.
This is the argument for a spread of values, so that at least one part is effective in each band. The spread should be chosen from the device’s switching spectrum rather than from a habit.
Power Plane Resonance
The plane pair between power and ground forms a cavity with its own resonances, and a capacitor placed at a resonant peak can be ineffective or, in a bad case, can shift the resonance rather than damp it. The behaviour depends on the board dimensions and the dielectric.
Where a design is sensitive, the plane resonances should be calculated and the capacitor placement chosen to damp them rather than to fill space evenly.
Return Path Continuity
The return current follows the path of least impedance, which at high frequency is directly under the signal or the supply trace. A break in the return plane forces the current to divert, and the diversion enlarges the loop and adds inductance.
Keeping the reference plane continuous under the supply path is therefore part of decoupling, and it is often the change that produces the largest reduction in noise.
Measurement and Verification
The verification is a measurement of the voltage at the device pins with the product running its worst case load, using a probe with a very short ground connection. A long ground lead measures the probe rather than the board.
Where the noise exceeds the device specification, the first changes are placement, via count and return continuity, in that order, because they are free and effective. Increasing capacitance is usually the last resort.
Documentation
The placement requirements should be part of the layout constraints rather than left to the layout engineer’s judgement, because the reason for the placement is not visible in the schematic. A note in the constraint file is worth more than a rule in a design guide.
Where a device has a published decoupling recommendation, it should be followed unless there is a reason to depart, and the reason should be recorded. Vendor guidance and layout reality are reconciled in the review described for design release.
Process Control and Verification
On a design of this kind, via placement is the item that decides how the rest of the board is arranged. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance. A stack-up that is drawn rather than described removes most of the ambiguity from a quotation, and it lets the fabricator price the board against the dielectric and copper weights that will actually be used.
Where the requirement is not written down, the shop supplies its own default, and the default is chosen for the process rather than for the design. The measurements that matter are the repeatable ones: conductor width and spacing, annular ring, finished hole size, plating thickness and surface finish are all verifiable on a coupon that travels with the panel.
Related reading: our fabrication notes, board quality and design release notes cover the same ground.
Process Control and Verification
On a design of this kind, via placement is the item that decides how the rest of the board is arranged. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance. A stack-up that is drawn rather than described removes most of the ambiguity from a quotation, and it lets the fabricator price the board against the dielectric and copper weights that will actually be used.
A first article check confirms that the process and the drawing agree on the points listed above, and that the coupon data supports the values used in the design.
Where a measurement falls outside the expected window, the sample is retained so that the cause can be established before the balance of the batch is released.
A first article check confirms that the process and the drawing agree on the points listed above, and that the coupon data supports the values used in the design.
Where a measurement falls outside the expected window, the sample is retained so that the cause can be established before the balance of the batch is released.
FAQ
Is a bigger capacitor always better for decoupling? No. Above its self resonance a larger part is inductive, so a smaller one is often more effective at the frequency of interest.
How many vias should a capacitor have? Two per terminal where space allows, because the inductance falls and the connection is shorter.
Does the capacitor need to be on the same side as the device? It does not, provided the via and plane path is short, and the same side is usually easier to keep short.
Can decoupling be fixed by adding capacitors later? Not if the loop is long, because the limiting factor is the inductance of the path rather than the capacitance value.
