ABF Substrate Shortage: The Constraint Behind AI Chips
The ABF substrate shortage has become the least visible constraint in the artificial intelligence supply chain. Industry surveys in August 2026 reported that demand for Ajinomoto build up film substrates tightened again as graphics processors, custom accelerators and co-packaged optics entered a new expansion cycle, with large chip vendors and cloud operators reported to be reserving capacity as far ahead as 2028 and encouraging suppliers to plan additions for 2029 and 2030. One report suggested the shortage that began in 2026 could widen further during 2027 and 2028.
Understanding why requires separating the substrate from the printed circuit board it sits on. A substrate is not a smaller version of a motherboard. It is the interface that translates the fine pitch of a semiconductor die to the coarser pitch of a system board, and it is manufactured with processes closer to semiconductor packaging than to conventional board fabrication.
What an ABF Substrate Does
A build up substrate consists of a core with alternating dielectric and copper layers, built up one at a time with fine lines and small vias formed by semi-additive plating. Its job is to fan out thousands of die connections into a footprint that can be soldered to a board, while distributing power and maintaining signal integrity at very high frequencies.
ABF refers to the insulating film used between copper layers, chosen because it can be processed into very fine features and because its electrical and mechanical behaviour is stable through repeated build up cycles. Producing it requires lithography, plating and inspection equipment that differs substantially from what board factories use.
Why the Bottleneck Moved Downstream
For two years the AI supply chain was described in terms of wafer capacity and advanced packaging. As those constraints eased through investment, the next limiting step became the substrate that the package sits on, and with it the materials and equipment used to make substrates.
This is a normal pattern in constrained systems: relieving one bottleneck exposes the next one downstream. What makes the current situation difficult is that substrate capacity cannot be expanded quickly. Building a substrate plant involves long equipment lead times, process development and customer qualification, and the equipment suppliers themselves are limited.
Package Area and Layer Growth
The reason demand rises faster than unit volume is that each package consumes more substrate. Accelerator packages have grown in area to accommodate more compute and more memory, and larger packages require more build up layers and more copper to route the connections and distribute power.
When package area grows and layer count rises, the substrate area consumed per chip increases on both counts, so a fixed amount of substrate capacity supports fewer chips each year. That relationship explains why capacity additions that look substantial in area terms can be absorbed without easing the shortage.
Finer Lines in Substrate Manufacturing
As die connection density rises, substrate line widths shrink toward the limits of semi-additive processing. Thin lines reduce side etch and improve yield, but they demand tighter control over plating thickness, resist application and development, and they place more of the electrical performance into the hands of the manufacturing process rather than the design.
Yield is the consequence. A substrate with thousands of fine lines and vias has many opportunities for a defect, and because the substrate carries an expensive die, a defective unit is discovered late in the process. Substrate manufacturers therefore invest heavily in inspection and in process control, which is also why their capacity cannot be replicated simply by buying similar equipment.
Co-Packaged Optics Adds Pressure
Co-packaged optics places optical engines next to the switch or accelerator die on the same package, moving high speed signalling from pluggable modules to the package itself. Reports indicate that the first generation of such switches began volume ramp during 2026, which multiplies the substrate requirement.
A co-packaged design integrates a switch application specific integrated circuit, optical engines and the interconnect between them into a compact assembly, so the substrate must route both very high speed electrical channels and the interfaces to the optical components. That combination raises layer count and precision together, at exactly the moment substrate capacity is short.
Who Is Reserving Capacity
When a constraint is expected to persist, large buyers respond by contracting further ahead. The reports describe multi year reservations by chip vendors and cloud operators and supplier plans extending to the end of the decade, which is a rational response for companies whose products depend on the substrate being available.
The effect for everyone else is that the available capacity shrinks before the shortage is visible in delivery dates. Smaller customers may continue to receive parts while the market is balanced and then discover that the capacity has been committed elsewhere, which is why monitoring lead times and booking positions matters more than monitoring price.
What the Projected Gap Means for Buyers
If the shortage widens in 2027 and 2028 as projected, lead times will extend and allocation will become the normal mode of supply. Design teams should assume that substrate availability constrains their schedule and plan accordingly, rather than treating it as a purchasing problem to be solved later.
Practical measures include designing for substrate options that are actually available, qualifying packages with more than one substrate source where the design allows it, and building schedule contingency into planning. Understanding where a package sits in the allocation queue is now as important as understanding component availability generally.
Substrate and Board Are Different Industries
Because both products use copper, dielectric and plating, it is easy to assume that board manufacturers could supply substrates if capacity were short. The processes differ enough that this is not realistic: line widths, panel sizes, plating chemistry, cleanliness requirements and inspection methods all diverge.
The practical connection between the two is at the package boundary. A board designer must route from the substrate footprint outward, meet the impedance and loss requirements of the package interface, and accommodate the thermal load that the package imposes. Getting that boundary right is a board level task, and it benefits from working with a manufacturer who understands how board capability interacts with packaging decisions.
Capacity Additions and Their Timing
Announced capacity additions take years to become usable volume. Equipment for fine line build up processing has its own lead times, plant construction takes time, and qualification with a specific customer package can take additional quarters. A plant that starts construction in 2027 will not relieve a shortage in the same year.
That timing mismatch is the mechanism behind cycles in constrained supply chains. Demand responds immediately to a shortage while supply responds with a delay, and when the new capacity arrives the market may have moved. For buyers the implication is that availability will improve later than the announcements suggest, and that forecasts should be built on qualification schedules rather than on construction schedules.
Implications for the Board Supply Chain
A substrate shortage does not stay confined to packaging. If accelerators cannot be packaged, the boards and systems that host them are not built either, so demand for high layer count boards, connectors and power components shifts rather than disappears.
Suppliers of system boards should therefore expect lumpy ordering patterns, with periods of allocation followed by bursts when package supply catches up. Planning capacity against a smooth demand curve in that environment leads to either idle equipment or missed deliveries, and it argues for flexible scheduling and for close communication with customers about their own package constraints.
Why Substrate Yield Is So Difficult
A substrate is built on a panel containing many units, and a defect anywhere in a unit makes it unusable. With thousands of fine lines, small vias and multiple build up layers, the probability of a defect accumulates across the structure, so yield depends on controlling every process step rather than on inspecting the finished part.
Material behaviour adds difficulty. Build up films are processed in repeated cycles of lamination, drilling and plating, and dimensional movement accumulates across those cycles, so registration has to be compensated at each stage. Manufacturers with mature processes achieve that through measurement and correction, and it is the reason a new plant cannot simply copy a design and expect the same result.
Interface Between Substrate and Board
The board side of the boundary is often the last thing designed and the first thing to cause trouble. The substrate footprint defines where signals leave the package, and the board must route from that footprint without introducing impedance discontinuities or excessive loss.
Power delivery crosses the same boundary, and the inductance of the connection between board and substrate affects how effectively decoupling on the board supports the die. Where the package is large and current is high, that inductance becomes a design constraint with its own measurement method, and it is best addressed with a manufacturer who can build the board and discuss the interface in the same conversation.
Planning Around a Structural Constraint
Substrate supply is now a structural feature of the AI hardware market rather than a temporary disruption. Designs that assume immediate availability of any package will be exposed when allocation tightens, while designs that anticipate it by keeping options open will keep shipping.
That argues for involving the manufacturing partner in package selection, verifying availability before a design is committed, and keeping qualified alternatives where the electrical design permits them. It also argues for a broader view of the manufacturing process that includes what happens after the board is built, because a board waiting for a package is not a finished product.
What to Watch
Three indicators will show whether the shortage is easing. The first is qualification announcements, which signal that new capacity is close to useful. The second is the lead time quoted by substrate suppliers, which reflects real allocation rather than announced intent. The third is package size and layer count trends, because demand grows with both and a continued increase will absorb capacity as fast as it is added.
For engineering teams the practical conclusion is that packaging is now part of the system design. Choosing a package, a substrate type and a board interface together, and confirming availability before committing a design, is the difference between a product that ships on schedule and one that waits for a component nobody expected to be scarce. Suppliers who can discuss that boundary in engineering terms, rather than in quality terms alone, are the ones worth involving early.
