EMC Fixes in PCB Layout: Return Paths First
Most boards that fail electromagnetic compatibility testing do so for reasons that were present in the layout from the first day, and the fixes are usually cheap if they are applied early and expensive if they are applied after the enclosure has been tooled.
Start With the Return Path
Every signal has a return current, and at high frequency that current follows the path of least impedance, which is the conductor directly beneath the signal rather than the shortest route to ground. Where the plane under a trace is interrupted, the return current is forced to detour, and the loop that it forms is the antenna that radiates.
The first review item is therefore continuity of the reference plane under every fast net. A slot, a plane split or a connector that forces the return through a via all break the continuity, and the fix is usually to stitch the planes or to move the offending route. Our mixed signal notes describe how the split is managed.
Slots and Splits
A ground plane is often split for good reasons, usually to separate a noisy digital return from a sensitive analogue one. The split itself is not the problem; the problem is routing a signal across it, because the return current then has no path except around the end of the split.
The rule that follows is simple: no trace crosses a plane split, unless the crossing is accompanied by a stitching capacitor or a bridge that gives the return current a path. Checking that rule mechanically, by overlaying the routing on the plane artwork, catches most of the mistakes. Our power integrity notes describe the related plane design.
Cable and Connector Interfaces
Cables are efficient antennas, and the current that leaves the board on a cable is often the current that fails the test. The usual remedies are a filter at the connector, a chassis connection that diverts the common mode current before it reaches the cable, and a layout that keeps the connector’s return path short and wide.
Where a connector carries a high speed differential pair, the pair should be routed as a pair all the way to the connector pins, and the shield or the return pins should be bonded to the chassis as close to the cable entry as the mechanical design allows.
Filtering and Its Placement
A filter only works if it is placed where the current it is meant to divert actually flows. A capacitor placed at the far end of a trace that carries noise will do very little, while the same capacitor placed at the point where the trace leaves the board does most of the work.
This is why the placement of filter components matters more than their values. A ferrite bead with the right impedance in the wrong place is less effective than a modest capacitor in the right one. Our ferrite bead notes describe how the impedance is chosen.
Clock and Switching Nodes
The highest frequency content on a board usually comes from a clock or a switching node, and both radiate in proportion to the area of the loop they close. Keeping a clock trace short, keeping its return directly beneath it, and keeping the switching node’s copper area small are the three measures that do most of the work.
Where a clock has to travel, it should travel on an inner layer between two planes rather than on the surface, because the planes contain the field. A surface clock trace with no adjacent plane is the single most common cause of a radiated emission failure.
Inductive Loads and Transients
Relays, motors and solenoids produce a transient when they switch off, and that transient will find its way onto the supply unless a path is provided for it. A diode across the coil, placed at the coil rather than at the driver, keeps the current loop local and prevents the transient from propagating.
The same reasoning applies to any load that is switched. The loop that carries the load current should be closed at the load, and the driver should see the load through a path that does not share its return with a sensitive circuit.
Reviewing the Layout for EMC
A structured review checks the same items every time: plane continuity under fast nets, absence of splits under crossing traces, connector filtering, clock routing and referencing, switching node area, and the placement of the transient suppression. That list is short enough to be applied mechanically.
The value comes from applying it before the board is made. A change to a plane on a drawing costs nothing, while the same change after the enclosure is built may require a new board, a new shield and a new test slot. Our design release checklist lists where the review belongs in the flow.
None of these measures require exotic materials. They require that the current has a short, continuous path home, and that the path is decided deliberately rather than left to the routing.
Process Control and Verification
Reviewing the design before the data is released is far cheaper than correcting it after the panel is in the tank, because every step downstream inherits the decision made at the front end. Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance.
The measurements that matter are the repeatable ones: conductor width and spacing, annular ring, finished hole size, plating thickness and surface finish are all verifiable on a coupon that travels with the panel. Documenting the assumption is part of the design work, and a short note on the drawing prevents a question that would otherwise arrive a day later and cost a day of schedule.
Where a value sits close to a process limit, the drawing should say so, since the shop can then open the process window rather than working to a nominal figure that carries no tolerance. Running a first article through the same checks as the production panel confirms that the two agree, and that comparison is the cheapest form of process control available at prototype stage.
FAQ
Does a four-layer board always pass EMC? No. A four-layer board gives the designer a continuous reference plane to work with, which removes the most common failure mechanism, but a design that splits the plane carelessly or ignores connector filtering can still fail. The stack helps; the layout still has to be right.
Is shielding a substitute for a good layout? It is a remedy rather than a substitute. Shielding adds cost, weight and assembly steps, and a shield over a board that radiates because of a split plane will attenuate the emission without removing its cause, which usually leaves a marginal result rather than a comfortable one.
What does gopcb check before a board is released? We check the plane continuity under the fast nets, the return path at each connector, the placement of filters and transient suppression, and the loop area of the switching nodes. Where the stack does not give us a continuous plane we say so at the stack-up stage rather than after the layout is complete.
