In DDR, MIPI, Ethernet, and RF PCB projects, changing a non-standard board thickness to a standard thickness can create a significant risk of impedance control problems. For example, directly changing a 1.7 mm non-standard PCB to a 1.6 mm standard thickness without reviewing the stackup may alter dielectric thickness and affect 50 Ω single-ended or 100 Ω differential impedance.
For high-speed designs, finished board thickness is not an isolated mechanical parameter. It is closely related to the stackup, dielectric thickness, copper thickness, dielectric constant, trace geometry, and reference-plane configuration.
Therefore, converting a non-standard thickness to a standard specification should not be treated as simply changing the finished-thickness value in PCB software. The key is to identify the impedance-sensitive dielectric layer, preserve its critical geometry whenever possible, and adjust thickness in less sensitive parts of the stackup.
This approach can reduce unnecessary routing changes while improving manufacturing compatibility and cost efficiency.
1. How Board Thickness Changes Affect Impedance
Controlled impedance depends on the electromagnetic geometry surrounding a transmission line.
For a microstrip, the relationship is influenced by:
- Trace width
- Copper thickness
- Dielectric thickness
- Dielectric constant (Dk)
- Trace-to-reference-plane distance
- Trace geometry
For a stripline, both the upper and lower dielectric structures contribute to the impedance.
As the distance between a signal trace and its reference plane changes, the electromagnetic field distribution also changes. Consequently, the characteristic impedance can shift even when the finished board thickness changes only slightly.
This is why engineers should distinguish between finished board thickness and the dielectric thickness that directly determines transmission-line geometry.
A useful classification is:
Impedance-sensitive dielectric layers:
Dielectric layers located directly between controlled-impedance traces and their reference planes.
Less impedance-sensitive dielectric layers:
Dielectric regions that are not directly responsible for the critical transmission-line geometry, such as some power-plane structures or mechanically adjustable portions of the stackup.
However, “less sensitive” does not mean electrically irrelevant. Changing any dielectric layer can affect overall stackup symmetry, power integrity, thermal behavior, via geometry, and other electrical characteristics.
The goal is therefore to identify which dimensions can be changed without violating the original electrical requirements.
2. Practical Example: Converting a 4-Layer High-Speed PCB to a Standard Thickness
Consider a four-layer PCB with the following original requirements:
- Finished thickness: 1.45 mm
- Outer-layer 50 Ω single-ended routing
- 100 Ω differential routing
- High-Tg FR-4 material
- 1 oz outer copper
- Controlled impedance required on the top layer
An example stackup could be:
TOP (1 oz) – PP 0.15 mm – GND – Core 0.90 mm – PP 0.15 mm – PWR – BOT (1 oz)
In this example, the top-layer signal traces are referenced to the adjacent ground plane. The 0.15 mm dielectric construction therefore forms an important part of the controlled-impedance geometry.
Suppose the PCB manufacturer recommends changing the 1.45 mm non-standard finished thickness to a standard 1.60 mm construction.
Instead of changing the entire stackup, the engineering team can first evaluate whether the impedance-sensitive dielectric structures can remain unchanged.
One possible approach is:
- Keep the TOP-to-GND dielectric structure unchanged.
- Keep the BOT-side reference structure appropriately balanced.
- Replace the internal core with a readily available standard thickness.
- Recalculate the complete finished thickness.
- Recheck impedance, stackup symmetry, and manufacturing tolerances.
For example, if the original 0.90 mm core can be replaced by an approximately 1.05 mm standard core while the critical PP structures remain unchanged, the finished thickness can move toward the required standard value without directly changing the top-layer trace geometry.
The actual material combination must always be confirmed against the PCB manufacturer’s available laminate and lamination data. The numerical values above are an engineering example rather than a universal stackup recommendation.
This type of PCB stackup optimization can potentially preserve existing routing and reduce engineering changes. Nevertheless, the revised stackup still needs to be recalculated and validated before production release.
3. What If the Impedance-Sensitive Dielectric Must Change?
Sometimes the desired standard thickness cannot be achieved without modifying a critical dielectric layer.
In this situation, the trace geometry should be recalculated rather than assuming that the original routing remains valid.
The general workflow is:
- Determine the new dielectric thickness.
- Confirm the actual Dk/Df of the selected material.
- Recalculate trace width and spacing.
- Recalculate single-ended and differential impedance.
- Check manufacturing tolerances.
- Perform SI simulation where appropriate.
- Add or retain an impedance test coupon.
- Verify the manufactured PCB using TDR or another suitable measurement method.
For differential pairs, both differential impedance and common-mode behavior should be considered. Changing the dielectric structure can alter the coupling between the two traces as well as their relationship with the reference plane.
Therefore, simply adjusting trace width until a nominal impedance value is reached may not be sufficient for demanding high-speed interfaces.
4. Special Considerations for 6-Layer and 8-Layer High-Speed PCBs
Six-layer and eight-layer boards usually contain a combination of microstrip and stripline structures. The stackup therefore becomes more sensitive to material and dielectric changes.
Maintain Stackup Symmetry
A symmetrical stackup can help reduce mechanical imbalance during lamination and thermal cycling.
When converting a non-standard thickness, engineers should evaluate whether the revised core and PP construction remains physically balanced around the board center.
Electrical optimization should not create a significant mechanical imbalance.
Preserve Stripline Dielectric Geometry
A stripline is affected by the dielectric structures above and below the signal layer.
If either dielectric thickness changes, the impedance can shift.
When modification is unavoidable, the upper and lower dielectric structures should be evaluated together rather than changing only one side without recalculation.
Control Dk and Df
For high-speed SerDes, RF, and other sensitive interfaces, material selection is just as important as physical thickness.
Changing to another PCB material with a different Dk can alter the characteristic impedance even if the dielectric thickness remains similar.
Df also affects dielectric loss and therefore insertion loss, especially as data rates and channel frequencies increase.
Material substitution should therefore consider:
- Dk tolerance
- Df
- Resin system
- Glass construction
- Copper roughness
- Moisture behavior
- Thermal stability
- Manufacturing compatibility
The target should not simply be “the same nominal Dk.” The actual material tolerance and the manufacturer’s controlled process should also be considered.
Review BGA Via Transitions
Changing stackup thickness can also affect via structures in BGA breakout regions.
A revised stackup may change:
- Via stub length
- Layer transition geometry
- Anti-pad dimensions
- Reference-plane transitions
- Local impedance discontinuities
For high-speed BGA interfaces, via-field modeling can therefore be necessary after a major stackup change.
5. Three Common Mistakes During Thickness Conversion
Mistake 1: Changing Only the Finished Thickness Parameter
One common mistake is to modify the finished board thickness in PCB design software while leaving the physical stackup unchanged.
The software value alone does not determine the material structure used during fabrication.
If the manufacturer subsequently substitutes cores or PP materials to achieve the requested thickness, the actual dielectric geometry may change and cause impedance deviation.
The physical stackup, not merely the thickness annotation, must therefore be reviewed.
Mistake 2: Selecting Materials With Different Dk
Another mistake is selecting a different core or PP simply because its thickness is convenient.
Even when the nominal dielectric thickness remains similar, a significant change in Dk can affect impedance.
For controlled-impedance designs, material substitution should therefore be evaluated through the complete stackup calculation.
Mistake 3: Relying Only on Simulation
Simulation is essential, but simulation alone cannot capture every manufacturing variation.
Actual impedance can be affected by:
- Lamination variation
- Copper thickness tolerance
- Trace etching
- Dielectric thickness variation
- Material Dk tolerance
- Glass-weave effects
- Registration
- Surface finish and plating
A production-ready design should therefore combine SI simulation, manufacturer stackup data, impedance coupons, and physical measurements where required.
6. Impedance Validation After the Stackup Change
A robust impedance control process should include both design verification and manufacturing verification.
Design Verification
Before releasing the revised design:
- Recalculate controlled-impedance traces.
- Verify Dk and Df.
- Check dielectric thickness.
- Review copper thickness.
- Confirm reference-plane continuity.
- Analyze differential-pair geometry.
- Review via transitions.
- Run SI simulation for critical interfaces.
Manufacturing Verification
During prototype or qualification builds:
- Include an impedance coupon when required.
- Verify the coupon construction corresponds to the actual signal layer.
- Measure impedance using TDR or an appropriate test method.
- Compare measured results with the design target and specified tolerance.
- Investigate systematic deviations before mass production.
The coupon should be designed so that its geometry and material environment represent the controlled-impedance structure as closely as practical.
7. Engineering Change and DFM Review Checklist
Before releasing a high-speed PCB with a new standard thickness, engineers should verify:
- The revised PCB stackup has been fully documented.
- Impedance-sensitive dielectric thicknesses have been identified.
- Core and PP materials are compatible with the required Dk/Df.
- Copper thickness remains within the electrical and manufacturing requirements.
- Single-ended and differential impedance have been recalculated.
- Critical DDR, USB, MIPI, Ethernet, or SerDes channels have been reviewed.
- SI simulation has been performed where necessary.
- Reference-plane continuity has been maintained.
- BGA via transitions have been reviewed.
- Via aspect ratio and plating capability have been checked.
- An impedance coupon has been included when required.
- BOM, fabrication drawings, stackup tables, and DFM review documents have been updated.
Conclusion
Converting a high-speed PCB from a non-standard thickness to a standard thickness is fundamentally an electrical and manufacturing engineering change, not simply a mechanical thickness adjustment.
The most effective strategy is to identify the impedance-sensitive dielectric layer first and determine which parts of the stackup can be modified without changing critical transmission-line geometry.
By maintaining controlled dielectric thickness where possible, selecting compatible PCB materials, recalculating impedance when changes are unavoidable, and combining simulation with physical impedance verification, engineers can reduce the risk of impedance drift while improving manufacturability.
For high-speed applications, every thickness conversion should ultimately be evaluated as a complete PCB stackup, signal-integrity, and manufacturing change. Kingda can support stackup optimization, impedance analysis, DFM review, prototype validation, and production engineering for high-speed multilayer PCB projects.
