I2C Bus PCB Design and Pull Up Selection
The I2C bus is attractive because it needs only two wires and a pair of pull up resistors, and it is used in almost every design that has a sensor, a memory or a small display. Its simplicity hides a set of constraints that appear as soon as the bus is long, the devices are many or the speed is raised. Most I2C problems are electrical rather than protocol problems.
How the I2C Bus Works
Both lines are open drain, which means every device can pull them low but none can drive them high. The pull up resistors restore the high level, and the resulting wired AND behaviour is what allows several devices to share the bus without contention. This is also why the bus is bidirectional without any direction control.
Every transfer begins with a start condition and ends with a stop, and each device has a unique address. addressing means that two devices with the same address cannot share a bus, which is a common problem with sensors whose address is fixed by the manufacturer and can only be changed by fitting a different part number.
The bus is also multi master, and arbitration allows two masters to begin a transfer at the same time: a master that loses arbitration detects the loss and retries later. In practice most systems have a single master, but the arbitration mechanism is still present and still affects the timing of the bus.
Pull Up Resistors and Rise Time
Because the high level is produced by a resistor charging the bus capacitance, the rise time is exponential rather than a controlled edge. The time to reach the logic high threshold is roughly proportional to the product of the pull up resistance and the bus capacitance, and the standard specifies a maximum rise time for each speed grade.
pull up resistor selection is therefore a compromise. A small resistor gives a fast rise and a large current when a device pulls the line low, while a large resistor reduces the current and slows the rise. The minimum value is set by the sink current rating of the devices on the bus, typically three milliamperes, and the maximum by the rise time requirement.
Where several devices are on the bus, each may have its own pull up, and the effective value is the parallel combination. A design that adds a module with its own pull ups to a board that already has them can end up with a resistor that is too small, producing a rise time that is fine but a low level that is too high because the device cannot sink the resulting current.
Bus Capacitance and Trace Length
bus capacitance is the sum of the pin capacitance of every device, the capacitance of the traces and the capacitance of any cable. The standard sets a limit of 400 picofarads for the conventional speed, and a bus that exceeds it will have rise times that violate the specification no matter how the pull ups are chosen.
Trace capacitance on a board is a few picofarads per centimetre depending on the geometry, which is modest, but the pin capacitance of a device can be ten picofarads and a cable can add fifty picofarads per metre. A bus with ten devices and a metre of cable reaches the limit quickly, and the design has to be evaluated against it rather than assumed to be acceptable.
Reducing the capacitance is possible in several ways: keep the traces short, avoid a long cable where a shorter one will do, and use a bus buffer that splits the bus into segments with its own capacitance on each side. A buffer also allows the two segments to run at different speeds, which is useful when one part of the bus is inherently slower.
Clock Stretching and Arbitration
clock stretching occurs when a device holds the clock line low to slow the transfer, which gives it time to process the data. It is part of the specification and every master must support it. A master that does not will produce intermittent failures with the devices that use stretching, and the symptom appears only under particular conditions of temperature or supply voltage.
Some devices hold the clock line for a long time during an internal operation, and the master must tolerate the delay rather than timing out. Where the timeout is not adjustable, the device may need to be operated differently, for example by using a different measurement rate, so that the internal operation completes faster.
Arbitration matters in systems with more than one master, and it relies on the open drain behaviour of the bus. A master that has lost arbitration must release both lines immediately. On a bus with a single master the mechanism is unused but the electrical requirements are unchanged.
Level Shifting and Multiple Voltage Domains
Devices on an I2C bus often run from different supplies, and a 1.8 volt sensor cannot simply be connected to a 3.3 volt bus. A dedicated bus translator is the correct solution: it contains the open drain switches required to join the two domains while keeping the pull ups on each side separate.
A common error is to use a general purpose level translator designed for push pull signals. Such a device contains a buffer that drives the line high, and on a bidirectional open drain bus that means contention with any device pulling the line low. If the bus locks up permanently at a low level, a push pull translator fitted to an open drain bus is one of the first things to check.
Where the two domains share a pull up through a resistor, the high level on the lower voltage side rises to the higher supply, which exceeds the absolute maximum rating of the lower voltage device. Every signal that crosses a domain boundary has to be checked against the supply of the device at the receiving end, and the general partition rules are described in mixed signal board design.
Layout of an I2C Bus
Keep the bus traces short and route them together, with the ground return alongside. A pair of bus lines running a long way around the board in different directions forms a large loop that both radiates and picks up interference, and the loop area is what determines the coupling to nearby switching circuits.
Place the pull up resistors close to the master rather than at the far end, and keep the stubs to each device short. On a bus that runs across several boards, provide a defined connector pinout with the ground alongside the signals, and consider a bus buffer at the entry point so that the capacitance of the external cable does not load the internal bus.
Keep the bus away from switching nodes and clock lines. The general methods for finding the path that interference takes into a slow signal are described in our article on EMI suppression design, and on an I2C bus the most common coupling path is a long parallel run alongside a switching supply trace. The documentation practices in manufacturable PCB design are useful for recording the bus topology so that it can be reviewed when a device is added later.
Debugging a Bus That Locks Up
Look at the two lines with a scope and trigger on the start condition. A bus where the clock line stays low indicates a device that is holding it, while a data line that remains low after a transfer indicates a device that did not release the bus. A single missing acknowledge is often the beginning of the sequence, so the trace should be examined from the start of the transfer rather than at the point of failure.
If a device holds the data line low, a bus recovery procedure consisting of clock pulses while the master releases the data line usually frees it. Building that recovery into the firmware is standard practice for a bus that connects to a device which can be reset independently, such as a sensor with its own brown out detector.
Check the rise time with a scope rather than by calculation. Measuring the time for the line to reach the high threshold, with the actual devices and the actual pull ups fitted, confirms whether the design has margin. A rise time close to the specified maximum is an indication that the bus capacitance is near the limit, and adding another device will push it over.
FAQ
How do I choose the pull up value? Start from the rise time requirement and the measured bus capacitance to find the maximum, then check the sink current at the minimum. Choose a value in between with margin at both ends.
Can I run I2C over a long cable? Only with a buffer or a bus extender. The standard capacitance limit is reached quickly with cable, and a longer bus will have rise times that violate the specification.
Why does the bus fail only when another device is fitted? The added pin capacitance increases the rise time, and the added pull ups change the effective resistance. Measure the rise time on the populated bus rather than on the bare board.
