Low Power SoC Board Design for Battery and IoT Products

Low power processors are marketed on their sleep current, but the board around them decides whether that number survives contact with a real product. A low power SoC board design has to deliver clean power to a fine-pitch package, hold leakage currents in the microampere range, and still support the interfaces the application needs. This article covers the layout and power planning decisions that keep a battery-powered design close to its theoretical budget.

Reading the SoC Datasheet Before Layout

Before drawing anything, extract four things from the datasheet: the supply rail list with tolerances, the maximum current per rail, the power sequencing order, and the package mechanical drawing with its recommended land pattern. Low power processors often integrate several regulators, so the external rail count may be smaller than the datasheet’s pin list suggests. Confirm which pins must be tied together and which must be filtered separately.

Also check what the device requires during reset and startup. Some processors specify a maximum ramp rate on a rail to prevent latch-up, and others require an external reference or a specific configuration pin level at the moment reset is released. These details do not appear in the block diagram, and they are the usual reason a first prototype fails to boot.

Power Rail Planning and Sequencing

Power rail planning starts from the current budget, not from the schematic. Build a table with the typical and peak current of each rail, then add the peripherals: radio module, sensor, display, storage. Group rails that share a voltage and a noise class, and keep analog or radio supplies separate from digital switching supplies. For a battery product, also record the efficiency of each regulator at the actual load current, because a converter that is 90 percent efficient at full load may be 60 percent efficient in sleep mode.

Sequencing matters when several rails power one die. Following the datasheet order prevents forward-biased protection structures and undefined internal states. If the processor integrates its own sequencer, the board only has to guarantee that the input rail is present and stable before enable. Where the board generates additional rails, chain the enables with defined delays and verify the order with a scope capture rather than by inspection.

BGA Escape Routing and Stackup Choice

BGA escape routing sets the minimum layer count. A fine-pitch package with a full perimeter of signals may need four layers even when the schematic is simple, because inner rows of balls must escape between the outer rows. Count the rows, apply the fabricator’s minimum trace width and clearance, and choose the stackup before routing begins. Changing from two to four layers after layout is a redesign, not an adjustment.

Keep the ground plane continuous beneath the processor and route high-speed signals on the layer adjacent to it. Wide power traces or planes reduce impedance and improve thermal performance. Review the escape pattern with escape routing and fanout rules so that via sizes and clearances are manufacturable at the volume you plan to build.

Decoupling Placement Discipline

Decoupling placement is where low power designs quietly lose their margin. Each supply pin needs a small capacitor as close as physically possible, with its own via to ground. Sharing one capacitor between two pins, or placing a capacitor on the far side of the board, lengthens the current loop and raises the impedance at high frequency. Place the smallest values closest to the pin and the bulk capacitance near the regulator output.

For fine-pitch packages, place capacitors on the same side as the processor when space allows, and use the inner layers for power distribution rather than for signal runs that could be routed elsewhere. If the processor has an integrated regulator requiring a specific inductor, keep that loop tiny and keep the feedback trace away from the switch node.

Sleep Current and Battery Life

Sleep current is dominated by leakage paths rather than by the processor. Pull-up resistors that stay connected to a powered rail, indicator LEDs, level shifters, and regulators with high quiescent current all consume energy while the product appears to be off. Audit every resistor connected to a supply and ask what it does during sleep. Replace fixed pull-ups with switched references where the signal allows, and choose regulators with quiescent current measured in microamperes, not milliamperes.

Isolation is the other lever. A load switch that disconnects a peripheral during sleep prevents that peripheral’s leakage from draining the cell, but the switch itself has a leakage specification that must be added to the budget. Measure the assembled board’s sleep current rather than estimating it, because a single wrong pull-up can double the figure. Plan the ground and power trace planning so the always-on domain stays physically small and easy to audit.

Peripherals, Interfaces and Cost

Every peripheral added to a low power board brings an interface and a power domain. Serial buses share pins well, but radio modules and displays often need dedicated control lines and a defined power sequence. Keep interface voltage levels consistent so that level shifters, which add both cost and leakage, can be avoided. Where shifters are unavoidable, select parts with a low quiescent draw and an enable pin.

Cost follows the same discipline. Fewer regulators, fewer unique component values and a smaller board outline reduce both material cost and assembly cost. Review the design against design guidelines for manufacturable boards before release, and confirm that the smallest dimensions used in the escape area are inside the fabricator’s standard process rather than its premium one.

Verification and Production

Verification for a battery product includes three measurements that are easy to skip: the current profile during each operating mode, the rail ramp and sequencing at cold temperature, and the sleep current of the assembled unit rather than of a bare board. Each of these catches a class of defect that a functional test will not reveal. Log the values so that production test can compare against a baseline.

gopcb builds low power and battery-operated boards from prototype to volume and can review the escape layout, the decoupling plan and the always-on domain before fabrication. A design review at that stage costs a few hours; discovering a leakage problem after the enclosure is molded costs a product cycle.

Estimating Battery Life from the Board

Battery life calculated from the processor datasheet alone is always optimistic. Build an energy budget from the duty cycle: time spent sleeping, time spent in each active mode, and the current drawn in each of those states by the processor, the memory, the radio and the sensors. Multiply each current by its duration, add the quiescent draw of the regulators, and divide the battery capacity by the total.

Then apply a derating factor for temperature and aging, because a lithium cell loses usable capacity at low temperature and after several hundred cycles. If the estimate is close to the product requirement rather than comfortably above it, revisit the duty cycle or the regulator efficiency before adding battery capacity, since a larger cell changes the mechanical design and the cost of the whole product.

FAQ

Is a two-layer board enough for a fine-pitch processor? Sometimes, but only when the ball count is low and the escape area can be routed on one layer plus a mostly solid ground plane. Once inner ball rows must escape, four layers are usually cheaper than trying to squeeze the routing into two.

How do I reduce sleep current quickly? Measure the current with the processor held in reset, then isolate subsystems one at a time using load switches or by removing components. The largest remaining contributor is usually a regulator’s quiescent current or a pull-up that was never meant to stay powered.

Do I need an external supervisor for a low power SoC? Only when the device does not include a reliable brownout detector with a defined threshold. If it does, an external supervisor adds leakage and cost for little benefit. Read the datasheet’s power-on reset description carefully before deciding.