PCB Design Pitfalls: A Senior Engineer’s Checklist
Most PCB design pitfalls are not exotic. They are ordinary assumptions that were correct on the previous project and wrong on this one, and they survive every review because everyone is looking at the parts of the board that changed. An experienced engineer’s checklist is really a list of the things that quietly carry over, and the discipline of checking them costs far less than the respin they prevent.
The Pitfalls That Survive Review
A design review concentrates attention on new circuitry, because that is where the novelty and the risk appear to be. The difficulty is that the failures usually come from the reused parts of the design: a footprint that was correct for the previous package variant, a stackup that was negotiated for a different layer count, a connector pinout that changed with the supplier’s revision. These are invisible precisely because nobody expects them to change.
The corrective habit is to treat reuse as a claim to be verified rather than a fact to be trusted. A footprint copied from an older library is a starting point, and comparing it against the current datasheet takes minutes. Doing that comparison for every reused part is dull, and it is the single most productive form of dullness available to a hardware team.
Footprint Assumptions
Footprints fail in three ways: the pad geometry does not match the package, the pin numbering is mirrored, or the courtyard is too tight for the assembly process. The first is a library accuracy problem, the second is a schematic symbol problem, and the third is a layout problem dressed up as a library problem. All three survive because the design tool reports no error when they are present.
Mirrored pin numbering is the most damaging, because the board can be electrically valid and still route awkwardly, hiding the error until the device is powered. A quick sanity check, drawing the package outline by hand next to the footprint, catches it faster than any automated comparison against a library that may share the same mistake.
Courtyard clearance deserves the same attention. A footprint that fits the pad geometry perfectly can still leave no room for the placement nozzle or the rework tool, and that failure appears at assembly rather than at design review. Checking the courtyard against the assembler’s requirements, not against the default in the library, is the reliable version of the check.
Stackup Drift Between Projects
A stackup is a negotiated document, and it is usually negotiated for one project at a time. When a new board inherits the previous stackup to save time, the dielectric thicknesses and the copper weights come along with it, but the impedance targets, the controlled nets and the fabrication tolerances may not suit the new design. The mismatch surfaces as impedance that is close to the target but consistently off in one direction.
The stackup is also where DFM constraints concentrate. Minimum dielectric thickness, aspect ratio for the finished holes, and the ratio of microvia diameter to depth are all process limits rather than design preferences, and a stackup that ignores them will be quoted with exceptions or rejected outright. Reviewing the stackup with the fabricator before layout closes is the cheapest part of the entire project.
Design Review Without a Checklist
An unstructured design review drifts toward whatever the loudest participant finds interesting. That is not a criticism of the participants; it is a property of meetings. A checklist fixes the scope by forcing the same questions to be asked on every board: power, clocks, resets, interfaces, mechanical constraints, test access and manufacturing limits.
The checklist does not have to be long. Ten categories, each with two or three specific questions, covers most of what goes wrong, and the value is in the repetition rather than in the sophistication. A review that answers the same ten questions every time produces comparable records, which is what makes the next review faster.
Pad and Solder Mask Details
Pad geometry is where the electrical and the manufacturing views of a board meet, and they do not always agree. A pad sized for the impedance calculation may be awkward to solder; a pad sized for reflow may add enough capacitance to disturb a fast net. Our notes on PCB pad design standards cover the standard compromises and the cases where the standard should be overridden deliberately.
Solder mask is a related trap. A mask opening that is larger than the pad helps soldering and hurts a controlled-impedance line; a mask dam that is thinner than the process can hold will be removed by the fabricator without discussion. Both of these are decisions that must be made in the design rather than discovered in the quotation.
Mechanical Interfaces and Board Outline
The board outline is usually the last thing to be drawn and the first thing to cause a problem. Mounting holes, connector positions, keep-outs around fasteners and the clearance between the board edge and the nearest copper all come from the mechanical model, and a small change there can invalidate routing that took a week.
Our notes on board outline and mounting design describe the clearances worth reserving for each class of hardware. Reserving them early costs a little area; discovering them late costs a redesign of the floorplan.
DFM Checks That Catch Real Problems
Design for manufacture is often treated as a compliance step at the end of the project, which is the least useful time to run it. The checks that matter are the ones performed when a change is still cheap: minimum annular ring, minimum trace and space against the chosen process, solder mask sliver removal, and the drill-to-copper clearance that decides whether a via can be placed there at all.
The practical approach is to run a lightweight DFM check at each layout milestone rather than a full audit once. Early checks catch the structural problems, and the final audit then only has to find the small residue that accumulated at the end, which is a much shorter conversation than the alternative.
Habits That Keep a Layout Honest
Senior engineers tend to converge on a few habits rather than a long procedure. They keep the schematic readable, because an unreadable schematic is the source of most connection errors. They route the constrained nets first. They keep a written record of the decisions they made deliberately, so that a later reviewer can tell the difference between a decision and an oversight.
Reviewing that record is the purpose of a formal design review process. Our notes on PCB design review process describe how to run one that produces findings rather than reassurance, which is the only outcome that changes the board.
FAQ
What is the most common PCB design pitfall? Reused footprints and stackups that were never re-checked for the current project. They are invisible to the design tool and cheap to verify, which makes them the highest-value item on any checklist.
When should DFM checks run? At every layout milestone, not only at the end. Early checks catch structural problems while they are still cheap to fix, and the final audit then has far less to find.
Can a checklist replace experience? No, it organises experience. A checklist makes sure the questions are asked; judgement is still needed to decide which answer is acceptable for the product being built at gopcb and elsewhere.
