Board Edge Clearance Rules Explained

Why the Edge Needs Clearance

The outline of a board is produced by routing, scoring or punching, and each of those operations has a tolerance and a mechanical effect on the material near the cut. Copper that reaches the edge can be torn, exposed, shorted by a burr or delaminated, and a component placed too close to the edge can be damaged by the profiling tool, by the depanelling operation or by the handling that follows. Edge clearance is therefore a set of rules that exist to protect the circuit from the process that shapes the board, not a stylistic convention.

Routing Tolerance and the Copper Keep-Out

The router removes material along the outline, and the finished edge can be expected to vary from the drawn outline by a tolerance that depends on the process. Copper must be kept back from the nominal outline by at least that tolerance plus a margin, so that the worst case still leaves a band of laminate between the copper and the edge. The minimum distance is usually given as a fabrication rule, typically in the region of 0.2 to 0.5 mm for a routed board, and it grows where the board is thick, where the profiling is done with a coarse tool, or where the edge will be handled heavily. Where a plane extends over the whole board, the plane pullback is what implements this rule, and it should be checked on every layer rather than only on the outer ones.

Components and the Courtyard

Components need their own clearance, larger than the copper clearance, because a placement machine and its nozzle need access and because the depanelling operation can stress the area near the edge. The component courtyard, which is the outline plus the placement tolerance and a small margin, should not cross the board edge, and for parts placed near an edge that will be broken out of a panel, the courtyard should also clear the tab and the break line. Where a connector is deliberately at the edge, the connector body is often allowed to overhang, but its pads and its contacts still obey their own clearance rules and the overhang has to be declared on the drawing.

Vias and Castellations

A via near the edge is a weak point, because the barrel is a hole in the laminate and the router can open it if it is too close, exposing the plating and creating a short or a mechanical defect. A via that must be exposed on the edge is a castellation and is designed as one, with its own geometry and its own tolerance. Where a plane is used for shielding and reaches the edge, a plated edge is usually required rather than an exposed plane, because a bare copper edge oxidises and is not solderable. The design rule for vias near the edge should be at least as large as the copper rule, and larger where the via is part of a high current path.

Copper Pullback by Process

The amount of pullback that is practical depends on how the edge is formed. A routed edge leaves a machined surface and needs a clearance that covers the router tolerance. A V-scored edge breaks along a line that is controlled by the blade and by how the panel is snapped, so the variation along the edge can be larger and the clearance should be increased. A punched edge is more repeatable but introduces shear stress that can damage features near the edge, so the clearance is set by the mechanical disturbance rather than by the dimensional tolerance. Where an edge is also plated, the plating process adds its own requirement, since the plating has to wrap around a surface with a defined geometry.

Connectors at the Edge

Where an edge connector or a card-edge interface is used, the copper deliberately reaches the edge and is defined by a separate set of rules covering the contact width, the pullback between contacts, the chamfer and the plating. These features are specified in the connector datasheet and should be copied from it rather than designed from a general rule. The rest of the board near a card edge still observes the normal clearance rules, and the transition between the connector area and the rest of the board is where mistakes occur, because the layout tool’s default clearance is often applied to the connector pads as well.

Panel and Depanelling Effects

The panel adds a second set of clearances. Tabs, V-score lines and the break line all remove or disturb material near the board edge, so a component or a via that is far enough from the outline can still be too close to a tab. Where the profile is a V-score, the break produces a burr on the edge, and a connector that has to slide into a mating part may not tolerate it. The panel drawing should be checked together with the board layout, and the tab positions should be chosen with the same attention as the edge clearance itself.

Clearance and Controlled Impedance

Edge clearance also interacts with impedance, because a trace that runs parallel to the board edge has a different environment on one side than on the other. The edge is a discontinuity in the reference, and a line that is close to it sees a changed return path and a changed impedance compared with a line in the middle of a plane. Where a design has controlled-impedance lines that must run near an edge, either the clearance should be increased until the effect is negligible, or the lines should be modelled with the edge present. The same reasoning applies to a plane that is pulled back from the edge: the reference is still present beneath the line, but the removal of the plane at the edge changes the return path for any current that would have flowed along the perimeter, which is one of the reasons shielding and edge plating are used together.

FAQ

How much copper clearance should there be from the edge? At least the profiling tolerance plus a margin, typically 0.2 to 0.5 mm on a routed board and more where the edge is scored or punched.

Can a component overhang the edge? Only deliberately, for a connector that is designed to, and it should be shown on the drawing with its own clearance rules.

Why are vias near the edge a problem? Because the router can open the barrel and expose the plating, which creates a short or a mechanical defect.

Is the clearance the same on every layer? No. Inner planes typically need a larger pullback than the surface, so it should be checked layer by layer.

Does the panel change the requirement? Yes. Tabs and score lines disturb material near the edge, so the panel has to be checked as well as the board.

Conclusion

Edge clearance protects the circuit from the operation that shapes the board, so it should be set from the profiling process and checked on every layer and against the panel as well as the outline. Keep copper back by the process tolerance plus a margin, keep courtyards inside the edge, treat exposed vias as castellations and copy card-edge geometry from the connector datasheet. Clearance rules are described under PCB capabilities, the profiling operations behind them in PCB manufacturing, and the layout constraints in PCB design and layout. Edge handling continues into PCB assembly in 2026.