Embedded Capacitor Design Guide

An embedded capacitor is a layer of dielectric placed between two copper planes inside the board, so that the planes and the material between them form a large distributed capacitor. It is not a replacement for every discrete capacitor on the board, and it is not a device that can be placed on a schematic in the usual way. It is a change to the power distribution structure, and it is designed as part of the stackup rather than as a component.

What the Layer Is

Two copper planes separated by a thin dielectric form a parallel plate capacitor. The capacitance is proportional to the area and to the permittivity of the material, and inversely proportional to the thickness of the dielectric between them.

An embedded capacitor uses a dielectric that is much thinner and has a much higher permittivity than the ordinary prepreg used between power and ground planes. The result is a capacitance per unit area that is several orders of magnitude higher than a conventional plane pair.

The layer is laminated into the board like any other layer, and it is usually placed directly under the surface layer that carries the high speed devices, so that the loop between the device and the capacitance is as short as the board allows.

Capacitance Density and What It Buys

The useful figure is capacitance density, expressed per unit area. A high density material gives more capacitance for the same board area, which matters because the area available under a device is fixed.

The benefit is in power integrity. A device that switches draws current from the nearest available source, and the loop inductance between the device and that source sets the voltage excursion. An embedded layer puts capacitance a few hundred microns away instead of at the edge of the board.

The layer does not replace the bulk capacitors, because its total capacitance is limited by the area. It replaces the high frequency decoupling and the small parts that have to be placed as close as possible to the pins.

The Trade Against Discrete Capacitors

A discrete capacitor can be chosen for its value, its voltage rating, its temperature characteristic and its equivalent series resistance, and it can be placed where the design needs it. An embedded layer has one value determined by the stackup and one characteristic determined by the material.

The advantage of the layer is that it has no solder joints and no placement inductance. A discrete part has an equivalent series inductance that is dominated by the mounting, and the mounting is often larger than the intrinsic inductance of the capacitor itself.

The disadvantage is the cost and the lead time. The material is expensive, it adds a lamination step and it is available from a limited number of suppliers, so the decision is usually justified by a specific electrical requirement rather than by a general desire for fewer parts.

Materials and the Stackup

The dielectric is supplied as a thin film that is laminated with the other layers. It is brittle compared with a normal prepreg, so the handling and the lamination cycle have to be controlled to avoid cracking, and the layer should not be placed where a mechanical stress is expected.

The thickness is a compromise. A thinner layer gives more capacitance and a higher risk of a breakdown or a handling defect, while a thicker layer is more robust and provides less capacitance.

The layer also changes the impedance of the planes. A power and ground pair with a thin dielectric has a low plane impedance at high frequency, which is the intended effect, and it changes the return path of the signals that reference those planes.

Design Rules

The layer should cover the area under the devices that need it and it should extend beyond them, because the capacitance at the edge of the plane is less effective than the capacitance directly under the load.

The vias that connect the layer to the surface must be short and numerous. A via that is long, or one that is shared with a different net, adds inductance back into the loop and cancels part of the benefit.

The layer should not be used as a signal reference unless the design accounts for it. A signal that references the embedded layer sees a different impedance from one that references a normal plane, and mixing the two references on a single net creates a discontinuity.

Fabrication Considerations

The material has a limited press cycle and a defined shelf life, and it has to be stored under the conditions the supplier specifies. A film that has absorbed moisture will blister during lamination.

The layer is thin, so the drilling and the plating have to be adjusted. A drill that passes through the layer can create a short between the two planes if the hole wall is not clean, and the drill parameters should be set for the material rather than for the board in general.

A short between the embedded planes is a board that cannot be reworked. The electrical test should therefore include a plane to plane resistance check with a limit that is tighter than usual, because a partial short is a defect that will grow.

Verification and Measurement

The capacitance of the finished layer can be measured at a test point on a coupon, and the value should be compared with the design figure. A layer that measures low may have a thickness that is out of specification or an area that has been reduced by a cut out.

The power integrity benefit is verified by measuring the noise on the power rail under a load step. The measurement should be made with a probe that does not itself add inductance, because a long ground lead will report the noise of the probe rather than the noise of the plane.

The plane to plane resistance and the breakdown voltage are the reliability measurements, and both should be part of the qualification of the material and of the process rather than of every board.

When to Use It

The layer is worth considering where a device has a fast load step, where the decoupling parts cannot be placed close enough, or where the board area is so constrained that the high frequency capacitors cannot be fitted.

It is less attractive where the power requirement is modest, where the board already has room for the capacitors and where the cost or the lead time of the material cannot be absorbed.

The decision should be made with a measurement or a simulation of the power impedance rather than by comparison with an unrelated design. The question is whether the impedance at the frequency of interest is low enough, and the layer is one of several ways to lower it.

Practical Rules

Place the layer under the load, connect it with short and numerous vias, and treat it as a stackup change rather than as a component. Verify the capacitance and the plane resistance on a coupon.

Record the stackup and the measurements with the build records and the power integrity data, and review the <a href="https://www.gopcba.com/pcb-laminate-material-properties/” title=”laminate properties”>laminate properties and the decoupling placement rules when the power impedance is analysed.

FAQ

Does an embedded capacitor replace the discrete decoupling parts? Only the high frequency ones. Its total capacitance is limited by the board area, so the bulk capacitors remain necessary.

What is the main advantage over a discrete part? The loop is very short and there is no solder joint or mounting inductance. The mounting often dominates the equivalent series inductance of a small discrete part.

Why is it a stackup decision? The value and the characteristics are set by the material and the layer thickness, not chosen per component, and the layer changes the plane impedance and the return path of referencing signals.