Network Interface PCB Design for High-Speed Links

What a Network Interface Board Carries

A network interface board connects a device to a network. It holds the controller or the switch silicon, the physical layer device, the magnetics and protection that separate the cable from the electronics, the connector, and often the power conversion that feeds the port. Wired Ethernet, fibre modules, and wireless interfaces all fall into the category, and each has its own layout priorities.

What they share is that the board carries differential signals at rates where the physical layout, not the schematic, decides whether the link works. A pair routed with unequal lengths or without a continuous reference will fail a compliance test that the same circuit passes on a reference design.

The Elements of the Interface

Copper Ethernet from ten megabits to a gigabit uses differential pairs that must be impedance controlled, usually to one hundred ohms differential, with a return path that stays continuous for the whole run. The magnetics module provides isolation and common-mode rejection; it is often integrated into the connector, but where it is discrete its placement determines how much of the cable’s noise reaches the PHY.

Fibre interfaces use a module cage with a high-speed serial interface to the host. These links run faster again, and the layout is dominated by loss, via transitions, and the reference plane under the differential pair. Wireless interfaces look different on the board but obey the same rules at the antenna feed, where a controlled impedance line and a clear keep-out region decide the range.

Power over Ethernet adds a power path to the same connector. The power pair carries current, often tens of watts, and the isolation and protection circuitry has to pass that current without disturbing the data pairs beside it.

Routing the Pairs

Each pair is routed as a pair, with the two traces the same length and kept close enough that they see the same environment. Length matching matters because a skew between the two conductors turns part of the differential signal into a common-mode signal, which increases emissions and reduces margin.

Symmetry matters as much as length. A pair that runs with one trace over a plane and the other beside a gap in it will have a different impedance on each conductor, and no amount of matching on the drawing fixes that. Splits in the reference plane are avoided under any high-speed pair, both because of the impedance discontinuity and because the return current has to detour.

Via transitions are minimised and, where they are needed, the two traces transition together with their return vias placed close by. Back drilling is used on thick boards where the remaining stub would cause a resonance inside the band of interest.

Ground, Reference and Stackup

A continuous ground plane under every signal layer is the foundation. It provides the return path, defines the impedance, and shields the pair from whatever is on the adjacent layer. Where the connector shell and the chassis ground meet the signal ground, the connection is made deliberately at one point rather than left to whatever copper happens to touch.

Stackups for these boards are arranged so that the high-speed pairs sit on layers adjacent to a plane and travel the shortest possible distance between the PHY and the connector. Four layers is adequate for a simple interface, six is common once several ports or a switch fabric are involved, and eight or more appear in aggregation hardware. Impedance is held within ten percent for general work, and within five percent where the link budget is tight.

Where the board also carries power delivery for the ports, the power layer is placed with enough separation from the pair layers to keep its switching noise out of the signal path, and the DC-DC converters are grouped at one edge rather than spread across the board.

Thermal behaviour is worth checking on ports that deliver power. A PoE port converts the cable voltage down to the device rail, and that converter dissipates several watts in a small area, so the copper beneath it, the thermal vias, and the air available around the connector decide whether it stays inside its rating. On multi-port hardware this is often what sets the board size rather than the routing.

Protection and Isolation

Ethernet interfaces have to survive electrostatic discharge, surges induced on long cables, and, in industrial installations, ground potential differences between equipment. Protection devices are placed at the connector so that the transient is diverted before it travels into the board, and their own return path goes directly to the chassis or the protective ground rather than through the signal ground.

Isolation is the other requirement, provided by the magnetics for copper Ethernet and by the module or a barrier for other interfaces. The isolation barrier is also a layout feature: keep the traces on either side of it physically separated, and make sure the creepage distance satisfies the standard the product claims.

Manufacturing Considerations

Impedance control is the main fabrication requirement, verified with coupons and time-domain reflectometry, and the fabricator has to hold the trace width and the dielectric height tightly because both contribute to the result. Fine-line capability is needed where the routing is dense, and controlled depth drilling or back drilling appears on thick backplanes.

Surface finish matters for the fine-pitch devices and for repeated insertion at the connector, so ENIG is common. Where the board will be handled in a rack environment, edge plating or a defined connector profile may be specified, and panelisation is designed so that the high-speed pairs are not routed close to the panel edge, where routing tolerances are loosest.

Testing

Electrical test confirms continuity and isolation, and impedance coupons confirm the stackup. Functional test then links the port up and measures error rates, which is the only check that catches a layout that is marginal rather than broken. Where the product claims compliance, the assembly goes through the applicable electromagnetic compatibility and interface testing, and it is worth doing a first-article link test with the actual cable and the actual partner device rather than a laboratory substitute. A fabricator experienced in PCB manufacturing for high-speed digital boards and a partner that can carry the assembly through PCBA testing together cover most of the practical risk.

FAQ

What impedance do Ethernet pairs use? Usually one hundred ohms differential, held within ten percent for general designs and five percent where the link budget is tight.

Why does length matching matter? Because skew between the two conductors of a pair converts part of the signal into common mode, which increases emissions and reduces the noise margin.

Can a network interface be built on four layers? Yes for a simple interface. Six or more layers become worthwhile once several ports, a switch fabric, or power delivery are on the same board.

Where do protection devices belong? At the connector, with a return path to chassis or protective ground that does not run through the signal ground.

How is the design verified? With impedance coupons for the stackup and live link testing with a real partner device for the layout and the firmware together.

Conclusion

A network interface board is a high-speed digital design with an analogue job to do at the connector. Continuous references, matched and symmetric pairs, a stackup that supports the impedance target, and protection that diverts transients before they reach the circuit are what make a link reliable at speed. For related reading, see our notes on PCB design and layout and telecommunications PCBA.