PCB Routing Rules That Keep a Layout Clean

Routing rules exist because the same mistakes appear on every board, and most of them can be prevented by a short list that the layout is checked against. A rule that is written down can be enforced by a design rule check, explained to a new engineer and reviewed on a schedule; a rule that lives only in someone memory is applied inconsistently. The rules below are the ones that most often decide whether a layout is manufacturable, testable and electrically sound.

Spacing, Width and Current

Minimum spacing is set by the fabrication process and by the voltage between the conductors, not by what the tool allows. Copper to copper clearance must be achievable across the whole panel, including at the corners where etching and plating behave differently, and it must satisfy the electrical requirement for the working voltage and the pollution degree of the product.

Width is set by three requirements at once: the impedance target for controlled nets, the current the trace must carry, and the process minimum. Where the three disagree, the widest requirement wins, and the stackup may need to change to satisfy an impedance that is incompatible with the current. Our notes on routing precision and edge quality describe how the finished width relates to the drawn width.

<img src="https://www.gopcba.com/wp-content/uploads/2026/08/Production-line-with-robotic-electronics-assembly-960×585-1.webp" alt="Routed multilayer PCB with continuous reference plane” />

Reference and Layer Changes

Every signal should have a reference plane adjacent to it and continuous beneath it for its whole length. Where a trace changes layers, the return current must change layers too, so a stitching via belongs beside the signal via. A layer change that also changes the reference plane is worse still, because the two references must be connected close by or the return current has no short path.

Plane splits deserve the same discipline. Treat a split as a wall that no trace may cross, and where a boundary is genuinely required, decide in advance which nets may cross it and where the two regions are joined. Most of the interference problems found during compliance testing trace back to a return path that was interrupted without anyone noticing. Our notes on mixed signal design guidelines cover the boundary case.

Vias, Pads and Escape Routing

Via selection is a manufacturability decision as much as an electrical one. A through via is cheap and reliable but consumes space on every layer it passes through, so a dense escape from a fine pitch package often needs smaller vias, filled and capped where they sit in a pad. The number of vias in a power path should be calculated from the current rather than inherited from a previous design.

Pad geometry has to respect the assembly process. A pad that is smaller than the component lead gives a weak joint, and one that is much larger than the lead encourages bridging between neighbours. Where a thermal pad or a fine pitch device is involved, the pad, the stencil aperture and the solder mask opening should be defined together rather than in three separate places.

Test Access, Silkscreen and Mechanical Fit

Test access is a design requirement, not an afterthought. Every net that is not directly accessible through a connector should have a probe point, and the point should be clear of components so that a fixture can reach it. Where a bed of nails will be used, the test vias should be on a consistent pitch and kept away from tall parts that would prevent the fixture from seating.

Silkscreen carries information that shortens assembly time and prevents mistakes: reference designators, polarity marks, pin one indicators and connector names. It must not sit on a pad, and where space is tight it should be trimmed rather than allowed to overlap the mask openings. The mechanical fit completes the list: mounting holes clear of copper, connector positions matching the enclosure, and component heights inside the available space. Our notes on board outline and mounting design cover the last of these.

Rules for Review and Enforcement

A rule that is not enforced is a suggestion. Most of the list above can be encoded in a design rule check, and the check should be run before release rather than during a crisis. The rules should reflect the capability of the shop that will build the board, because a design that passes a default check may still sit outside the process window of the supplier actually chosen.

The rest belongs in a review. Someone other than the author should look at the escape routing from the largest package, the return path under the fastest nets, the thermal path from the power stage and the placement of the test points. Checking a short list with a purpose is more effective than a general inspection, and it is far cheaper than a board revision. Our notes on the PCB design process show where the review fits.

FAQ

What is the most important routing rule? Keep the reference plane continuous under every signal. Most other geometry problems are recoverable, but an interrupted return path creates radiation, sensitivity and impedance problems at the same time.

How wide should a trace be? Wide enough for the current it carries, correct for the impedance it must present and no wider than the space allows. Where those conflict, the stackup or the layer assignment usually has to change rather than the rule.

Should every net have a test point? Every net that cannot be reached through a connector should, ideally. Test access planned at layout time costs a little board area; test access added later costs a revision and a new stencil.

Trace Spacing and Crosstalk

Trace spacing serves two purposes: it satisfies the voltage clearance requirement and it controls coupling between neighbours. The coupling falls roughly with the square of the separation until the reference plane begins to dominate, so increasing trace spacing is a cheap way to reduce crosstalk on a bus without changing the stackup. Where the routing is too dense for generous spacing, moving the signals closer to the plane achieves a similar result by containing the field.

The sensitivity of the victim matters as much as the aggressiveness of the source. A reset line, an interrupt or a precision analogue input should not run parallel to a clock for any distance, and where a crossing is unavoidable it should be at right angles. Length of parallel run is the parameter to watch, because coupling accumulates with distance even when the spacing is fixed.

Documenting and Maintaining the Rules

A rule set is only useful if it is written down and kept current. The document should state each rule, the reason behind it and the check that verifies it, so that a future engineer can tell whether the rule still applies when the process changes. Rules that came from a particular vendor capability should be labelled as such, because they become wrong the moment the vendor changes.

Maintaining the list is equally important. Fabricators improve their tolerances, packages shrink and the interfaces a product must support change, so the rules should be reviewed periodically and updated with evidence from real builds. Recording which rule caused a problem on a specific project is the most effective way to justify a change, and it turns a document that nobody reads into one that people trust.