PCB Stack-Up: Layer Assignment and Reference Planes

A stack-up fixes dielectric thickness, copper weight, layer order and the distance between each signal layer and its reference plane. Those choices set the impedance of every controlled net, the coupling that produces crosstalk, and the mechanical balance of the board before a single trace is routed. This article covers what each decision controls, and what the stack-up drawing has to state so the fabricator can build what the design assumes.

What a Stack-Up Decides

The stack-up is the only document that fixes impedance, return path geometry and board thickness together, and everything downstream inherits it. A layer assignment that places a signal layer far from its plane cannot be repaired by layout, because the distance is a property of the construction rather than of the routing.

A stack-up that is drawn rather than described is the only version a fabricator can build to. When the drawing shows a nominal 0.1 mm dielectric, the shop will use the closest prepreg it stocks, which may be 0.108 mm, and the impedance moves with it.

Reference Planes and Return Paths

Every signal current returns through the nearest plane, and the return follows the path of least inductance, which means it runs directly beneath the trace. Splitting that plane forces the return to detour, and the detour is an inductance that appears as noise and as radiated emission.

The practical rule is that a signal layer should sit beside an uninterrupted plane, and that a plane split under a signal is a routing error rather than a stack-up error. Checking splits at layout review is cheaper than finding them in an EMC chamber. The laminate choices involved are described in our laminate material notes.

Return current follows the trace, not the plane as a whole, so a plane that is nominally continuous but crossed by a slot behaves exactly like a split plane.

Layer Count and Symmetry

The layer count follows from routing density and from the number of planes required, but symmetry is what keeps the board flat. A build with more copper on one side of the centreline bows during lamination and again during reflow, and the assembly process cannot correct it. The measurement side is covered in our warpage guide.

Symmetry means matching copper weight and dielectric thickness about the centre of the build, not merely using the same number of layers on each side of it. Where symmetry is impossible, the fabricator should be told which side may carry the imbalance so that it can be managed rather than discovered.

Dielectric Thickness and Impedance

Controlled impedance depends on trace width, dielectric thickness and dielectric constant, and on nothing else the designer can change once the drawing is released. A 50 ohm microstrip on 0.1 mm of 4.3 dielectric needs a trace about 0.19 mm wide, and the same trace over 0.15 mm needs roughly 0.28 mm.

The tolerance on thickness matters as much as the nominal value. A dielectric specified at plus or minus 10 percent moves the impedance by several ohms, so the drawing should state the thickness tolerance, the resulting impedance band, and the coupon that will be used to confirm it.

Crosstalk and Layer Spacing

Crosstalk falls with the square of the distance to the reference plane and rises with the parallel length between traces. Placing a signal layer close to its plane reduces the field reaching a neighbouring trace, which is why thin dielectrics are used on high speed layers even when the impedance could be met with a thicker one.

Edge coupling between the two outermost traces of a bus is usually worse than between interior pairs, because an edge trace has a neighbour on one side only. Adding a ground trace beside the bus, or increasing the spacing to twice the trace width, removes most of that effect.

Plane Pairs and Power Integrity

A power plane and a ground plane placed close together form a distributed capacitance that supplies high frequency current and lowers the plane impedance. Two planes separated by 0.1 mm offer roughly ten times the capacitance of the same pair separated by 0.5 mm, which is a change worth making in the stack-up rather than in the capacitor list.

The spacing also sets the resonant behaviour of the plane pair, so the choice belongs with the decoupling study rather than being left to whatever thickness balances the build. Where the stack-up cannot place the pair close together, the decoupling network has to cover a higher frequency range.

Plane pair spacing is one of the few high frequency decisions that costs nothing to change on paper and a great deal to change after the boards are ordered.

Mixed Signal and Analogue Areas

An analogue section needs a quiet reference, and the usual approach is a separate ground area connected to the digital ground at one defined point. The stack-up has to provide the layer that carries it without breaking the digital return path beneath the digital traces.

Where one plane serves both, layout controls the result rather than the stack-up: analogue traces kept over the analogue area, and digital return currents steered away from it. The partition should be drawn so that it is not bridged later by a shield or a fastener.

Buried and Blind Structures in the Stack

Adding a blind or buried via changes which layers can be connected without a through hole, and it changes the drill schedule and the lamination stages. The stack-up drawing should state which layer pairs are joined by which drill, because the fabricator builds the sequence from that information. Structures of this kind are described in our multilayer processing notes.

A stack-up that mixes a buried via between layers two and three with a through via from one to four has to be laminated in more than one stage, which changes both lead time and cost. Those structures belong in the design review rather than in a note added after the quotation.

Documentation and Verification

The stack-up drawing states layer order, copper weight, dielectric material and thickness with tolerance, finished board thickness, and the impedance requirements with the coupon that applies. A note requiring a cross-section coupon from the same panel completes it, following the practice in our fabrication notes.

The fabricator’s confirmation should come back as a drawing with actual materials and thicknesses, and that confirmation is what the impedance coupon is checked against. When it is not requested, the first evidence that the stack-up was built differently arrives with the finished boards.

FAQ

Can the impedance be corrected in layout if the stack-up is wrong? Only within the range that trace width can compensate for, and the width needed may not fit the routing. The stack-up is the cheaper place to fix it.

How far should a signal layer be from its plane? Close enough that the field is concentrated between the trace and the plane, which in practice means the dielectric under the trace is the thinnest one the impedance target allows.

Does a plane split always break the return path? Yes, for any signal crossing it. A return current cannot follow a trace across a slot, so it detours and the loop area grows with it.