What Makes A PCB Design High Speed

The label high speed is applied to boards, interfaces and design teams, and it rarely means the same thing twice. For a layout engineer it usually describes a set of constraints; for a component vendor it describes a data rate; for a test engineer it describes what the equipment has to keep up with. The useful definition is the one that determines which layout rules apply, and that is based on time rather than on rate.

This article sets out a working definition, the quantities that decide whether a net is affected by transmission line behaviour, and the practical consequences for a design team.

Getting the definition right prevents two opposite errors: treating a slow design as though it were fast, and treating a fast design as though the rules of thumb that worked before still applied.

The Definition That Matters

A net behaves as a transmission line when the time taken for a signal to travel its length is comparable to the rise time of the edge. The usual threshold is one sixth of the rise time, above which the reflection returns as a separate event and the waveform at the receiver departs from the waveform at the driver.

Everything follows from that ratio. A long trace with a slow edge may be below the threshold, and a short trace with a very fast driver may be above it. That is why a board can be described as high speed because of one interface and ordinary because of another, and why the constraint set should be applied per net class rather than to the design as a whole. The characteristic impedance of a net only becomes relevant once the criterion is met.

Rise Time Is A Property Of The Driver

The edge rate is set by the output stage of the driving device, and modern devices are fast regardless of the data they carry. A microcontroller pin toggling a status line can have an edge measured in hundreds of picoseconds, which makes a ten centimetre trace on an ordinary board behave as a transmission line even though the signal changes state a few times a second.

This is the reason low speed interfaces surprise designers. The data rate sets how often the line is exercised; the driver sets how much high frequency content the exercise contains. When a board fails emissions or shows ringing on a slow bus, the driver’s edge rate is usually the explanation.

Consequences For The Stackup

Once a design contains nets above the threshold, the stackup becomes an electrical structure rather than a mechanical one. Signal layers need adjacent planes, the dielectric thicknesses have to be chosen to produce the required impedances, and layer pairs have to be arranged so that routing and reference can be planned together.

This changes the order of the design work. The stackup is chosen before the layout, on the basis of the number of controlled impedance nets, the number of routing layers required and the materials available. The arrangement of layers from four to eight is a design decision in the same way that a component value is.

Consequences For Routing

Routing becomes a matter of maintaining the environment rather than connecting the netlist. A trace must have a continuous reference, its impedance must be held along its length, its discontinuities must be short, and its coupling to neighbours must be controlled. Each of these is a rule that can be expressed and checked.

The rules are not confined to the fast nets. A slow net routed beside a fast one can be a victim of coupling, and a slow net crossing a plane boundary can create a return path problem for the fast net beside it. The spacing rules used to control crosstalk apply to the victim as much as to the aggressor.

Consequences For The Process

A high speed design also constrains fabrication. Controlled impedance requires the fabricator to hold geometry to a tolerance and to provide test coupons, and the material choice narrows the list of suppliers who can build the board. Both add cost and lead time, which is why the classification should be based on the criterion rather than on caution.

Where the design sits near the boundary, the decision should be made deliberately and recorded. Marking every net as controlled impedance costs money, and marking none of them leaves the marginal nets to chance.

The classification is not permanent. A design that was ordinary on one process may become marginal on the next if the driver is replaced with a faster part during a cost reduction, because the edge rate changes and the criterion is applied again. Reviewing the net classification whenever a device changes is a cheap habit that catches a whole class of regression.

Consequences For Verification

Verification changes as well. A high speed design needs measurements that a slow design does not: impedance on a coupon, insertion loss for a long channel, and an eye diagram at the receiver for the interfaces that are marginal. These are more demanding than a functional test and should be planned as part of the design rather than added at the end.

The equipment and the fixtures for those measurements take time to prepare, and a design that reaches the verification stage without provisions for probing will spend longer there than the design itself required.

It is also worth distinguishing between a net that is fast and a net that is sensitive. A sensitive net is one whose disturbance matters, such as an analogue reference or a low level sensor input, and it may need protection from coupling even though its own edges are slow. The two categories often require different treatment: the fast net needs a controlled environment, the sensitive net needs isolation.

Applying The Definition

A practical approach is to list the interfaces, record the rise time of the driving device and the longest route for each, and mark the ones that exceed the threshold. The result is a short list, and that list determines which nets have to be impedance controlled, which stackup is required, and what the verification plan must cover.

That list is also the answer to the question of whether the design is high speed. A design is high speed when the list is not empty, and the entries on the list are what has to be treated carefully.

Finally, the definition should be recorded in the design documentation rather than held in the designer’s head. A short table listing each interface, its driver edge rate, its longest route and whether it exceeds the threshold makes the design self describing, and it lets the next engineer apply the same criteria without re-deriving them.

FAQ

Is a design high speed if it has a fast clock? Not necessarily. A fast clock with a slow driver and a short route may be entirely ordinary, while a slow interface with a fast driver and a long route may not be.

Does a low speed board need a ground plane? It benefits from one for emissions and for return path reasons, but it does not need controlled impedance unless a net exceeds the criterion.

Which net class usually exceeds the threshold first? The clock and any interface with a fast differential driver, because their edges are the fastest on the board and their routes are usually the longest.